8 Commits

Author	SHA1	Message	Date
James E. Stine	15d38f8c7f	Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines ... Katherine/James	2021-12-29 12:59:17 -06:00
David Harris	865d5ce0b1	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
David Harris	ecce1e62ee	changed ideal memory to MEM_DTIM and MEM_ITIM	2021-12-14 13:05:32 -08:00
Ross Thompson	5642918ead	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
Ross Thompson	f4c221f20a	Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.	2021-11-17 12:47:19 -06:00
Ross Thompson	23e78c4842	Fixed uart by reversing the bit order on transmit. ... Set prescale to 0.	2021-11-17 10:32:41 -06:00
Ross Thompson	f6c6cb9ed2	Merge branch 'main' into fpga	2021-10-11 18:17:58 -05:00
Ross Thompson	9150133c7d	Fpga simualtion files.	2021-10-11 10:24:40 -05:00