Github_Repos/cvw
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Author SHA1 Message Date
David Harris
b9e3ab7e1e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-19 14:08:24 -07:00
David Harris
a88af1841f radix 2 SRT checkin 2021-10-19 14:08:16 -07:00
bbracker
af998e3e27 gitignore the addins folder because it contains external repos 2021-10-19 13:32:26 -07:00
James E. Stine
41010aa418 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
James E. Stine
a75abb04bd Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00
Ross Thompson
d11136c406 Fixed bug with the external memory region selection. 
Updated bios program to copy just 127MB to dram.
 2021-10-19 11:23:23 -05:00
David Harris
3bc985d230 Changed some flops to settable 2021-10-18 17:05:29 -07:00
David Harris
cc2b5eeed9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 16:54:08 -07:00
David Harris
0516ee768b replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
davidharrishmc
0bb1c1c23c Update README.md 2021-10-18 16:23:22 -07:00
David Harris
398337951d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 15:44:31 -07:00
David Harris
00d8035836 Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
Ross Thompson
5ce58b35a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-18 17:25:48 -05:00
Ross Thompson
cd58a388e4 fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
davidharrishmc
e681020d9e Update README.md 2021-10-18 13:43:10 -07:00
davidharrishmc
197a8ca7e9 Update README.md 2021-10-18 13:39:40 -07:00
davidharrishmc
d03e42fe95 Update README.md 2021-10-18 11:17:24 -07:00
davidharrishmc
7a36c48ac9 Update README.md 2021-10-18 09:52:40 -07:00
James E. Stine
37fe5e56a8 Sanitization some more on mult_cs.sv 2021-10-18 05:24:16 -05:00
James E. Stine
d0ab43e4e8 Update some on mult_cs and delete DW02_mult.v 2021-10-18 05:06:49 -05:00
James E. Stine
de7b673e34 Add hacky hand-made carry/save multiplier - will improve 2021-10-16 10:37:29 -05:00
Katherine Parry
c34633804a cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
c5b99300e7 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
869c35ba1c Fixed typo in imperas64mmu tests causing PMP tests not to run. 2021-10-14 13:42:24 -07:00
Skylar Litz
71397d5db9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
4ca4e13ba2 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
kipmacsaigoren
a898204c04 added outputs from synth run to test mul changes 2021-10-13 12:38:14 -05:00
bbracker
bfe972a213 gitignore new logs folder 2021-10-12 10:42:13 -07:00
bbracker
4abc6fc915 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
Shreya Sanghai
4424006624 added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
Katherine Parry
b79021a73e lint warnings fixed 2021-10-12 09:45:02 -07:00
Katherine Parry
539d21645f some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
kipmacsaigoren
7873ba7867 added historical outputs folder for synth runs 2021-10-11 19:52:52 -05:00
Ross Thompson
f6c6cb9ed2 Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Ross Thompson
b3694bfdfd Fixed boot loader program to start at correct address. 
modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
 2021-10-11 17:22:23 -05:00
Shreya Sanghai
0acf9fd746 made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
84ff2b49c7 actually added redundant mul 2021-10-11 11:29:13 -07:00
David Harris
af7903e1b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 11:21:39 -07:00
David Harris
1cdc5db75d Extended lint to check rv32/64g (including fpu. Not clean yet. 2021-10-11 11:20:42 -07:00
Shreya Sanghai
a1c9ffdf2b added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
ab6a796690 Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
Ross Thompson
f1eda1bf6f Fixed sdc byte and nibble orders. 2021-10-11 12:15:52 -05:00
davidharrishmc
76e186693c Update README.md 2021-10-11 08:50:44 -07:00
Ross Thompson
9150133c7d Fpga simualtion files. 2021-10-11 10:24:40 -05:00
Ross Thompson
bfe633d087 Partially working sd card reader. 2021-10-11 10:23:45 -05:00
David Harris
8a39f37f94 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 08:14:38 -07:00
David Harris
f1190b6ceb intdiv cleanup 2021-10-11 08:14:21 -07:00
davidharrishmc
fa2c6bf381 Update README.md 2021-10-11 08:13:15 -07:00
David Harris
4139f27d10 Divider FSM simplification 2021-10-10 22:24:14 -07:00