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Fixed boot loader program to start at correct address.

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modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
This commit is contained in:
Ross Thompson 2021-10-11 17:22:23 -05:00
parent f1eda1bf6f
commit b3694bfdfd
5 changed files with 107 additions and 19 deletions
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2
testsBP/fpga-test-sdc/copyFlash.c
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@ -33,7 +33,7 @@ void copyFlash(long int blockAddr, long int * Dst, int numBlocks) {
int index;
for(index = 0; index < numBlocks; index++) {
copySDC512(blockAddr+(index*512), Dst+(512/8));
copySDC512(blockAddr+(index*512), Dst+(index*512/8));
}

2
wally-pipelined/src/sdc/SDC.sv
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@ -352,7 +352,7 @@ module SDC
.o_ERROR_CODE_Q(ErrorCode),
.o_FATAL_ERROR(FatalError),
.i_COUNT_IN_MAX(-8'd62),
.LIMIT_SD_TIMERS(1'b1)); // *** must change this to 0 for real hardware.
.LIMIT_SD_TIMERS(1'b0)); // *** must change this to 0 for real hardware.
endmodule

76
wally-pipelined/src/sdc/sd_top_wrapper.v Normal file
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@ -0,0 +1,76 @@
module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8)
(
input clk_in1_p,
input clk_in1_n,
input a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
// io_SD_CMD_z : inout std_logic; // SD CMD Bus
inout SD_CMD, // CMD Response from card
input [3:0] i_SD_DAT, // SD DAT Bus
output o_SD_CLK, // SD CLK Bus
// For communication with core cpu
output o_READY_FOR_READ, // tells core that initialization sequence is completed and
// sd card is ready to read a 512 byte block to the core.
// Held high during idle until i_READ_REQUEST is received
output o_SD_RESTARTING, // inform core the need to restart
input i_READ_REQUEST, // After Ready for read is sent to the core, the core will
// pulse this bit high to indicate it wants the block at this address
output [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
// being published
output o_DATA_VALID // held high while data being read to core to indicate that it is valid
);
wire CLK;
wire LIMIT_SD_TIMERS;
wire [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX;
(* mark_debug = "true" *) wire [4095:0] ReadData; // full 512 bytes to Bus
wire [32:9] i_BLOCK_ADDR; // see "Addressing" in parts.fods (only 8GB total capacity is used)
wire o_SD_CMD; // CMD Command from host
wire i_SD_CMD; // CMD Command from host
wire o_SD_CMD_OE; // Direction of SD_CMD
(* mark_debug = "true" *) wire [2:0] o_ERROR_CODE_Q; // indicates which error occured
(* mark_debug = "true" *) wire o_FATAL_ERROR; // indicates that the FATAL ERROR register has updated
(* mark_debug = "true" *) wire o_LAST_NIBBLE; // pulse when last nibble is sent
assign LIMIT_SD_TIMERS = 1'b0;
assign i_COUNT_IN_MAX = -8'd62;
assign i_BLOCK_ADDR = 23'h0;
clk_wiz_0 clk_wiz_0(.clk_in1_p(clk_in1_p),
.clk_in1_n(clk_in1_n),
.reset(1'b0),
.clk_out1(CLK),
.locked(locked));
IOBUF SDCMDIODriver(.T(~o_SD_CMD_OE),
.I(o_SD_CMD),
.O(i_SD_CMD),
.IO(SD_CMD));
sd_top #(g_COUNT_WIDTH)
sd_top(.CLK(CLK),
.a_RST(a_RST),
.i_SD_CMD(i_SD_CMD), // CMD Response from card
.o_SD_CMD(o_SD_CMD), // CMD Command from host
.o_SD_CMD_OE(o_SD_CMD_OE), // Direction of SD_CMD
.i_SD_DAT(i_SD_DAT), // SD DAT Bus
.o_SD_CLK(o_SD_CLK), // SD CLK Bus
.i_BLOCK_ADDR(i_BLOCK_ADDR), // see "Addressing" in parts.fods (only 8GB total capacity is used)
.o_READY_FOR_READ(o_READY_FOR_READ), // tells core that initialization sequence is completed and
.o_SD_RESTARTING(o_SD_RESTARTING), // inform core the need to restart
.i_READ_REQUEST(i_READ_REQUEST), // After Ready for read is sent to the core, the core will
.o_DATA_TO_CORE(o_DATA_TO_CORE), // nibble being sent to core when DATA block is
.ReadData(ReadData), // full 512 bytes to Bus
.o_DATA_VALID(o_DATA_VALID), // held high while data being read to core to indicate that it is valid
.o_LAST_NIBBLE(o_LAST_NIBBLE), // pulse when last nibble is sent
.o_ERROR_CODE_Q(o_ERROR_CODE_Q), // indicates which error occured
.o_FATAL_ERROR(o_FATAL_ERROR), // indicates that the FATAL ERROR register has updated
.i_COUNT_IN_MAX(i_COUNT_IN_MAX),
.LIMIT_SD_TIMERS(LIMIT_SD_TIMERS)
);
endmodule

12
wally-pipelined/src/sdc/tb/ram2sdLoad.py Executable file
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@ -0,0 +1,12 @@
#!/usr/bin/python3
import sys, fileinput
address = 0
for line in fileinput.input('-'):
# the 14- is to reverse the byte order to little endian
formatedLine = ' '.join(line[14-i:14-i+2] for i in range(0, len(line), 2))
sys.stdout.write('@{:08x} {:s}\n'.format(address, formatedLine))
address+=8

34
wally-pipelined/src/uncore/dtim.sv
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@ -53,7 +53,7 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
initial begin
//$readmemh(PRELOAD, RAM);
RAM[0] = 64'h9441819300002197;
RAM[0] = 64'h9461819300002197;
RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301;
RAM[3] = 64'h4681460145814501;
@ -77,23 +77,23 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
RAM[21] = 64'h11010002806702fe;
RAM[22] = 64'h84b2842ae426e822;
RAM[23] = 64'h892ee04aec064505;
RAM[24] = 64'h06c000ef07c000ef;
RAM[25] = 64'h979334fd02905463;
RAM[24] = 64'h06e000ef07e000ef;
RAM[25] = 64'h979334fd02905563;
RAM[26] = 64'h07930177d4930204;
RAM[27] = 64'h94be200909132004;
RAM[28] = 64'h2004041385ca8522;
RAM[29] = 64'hfe941ae3014000ef;
RAM[30] = 64'h690264a2644260e2;
RAM[31] = 64'h2783674980826105;
RAM[32] = 64'h3823dfed8b851047;
RAM[33] = 64'h10f72423479110a7;
RAM[34] = 64'h8b89104727836749;
RAM[35] = 64'h674920058693ffed;
RAM[36] = 64'hbc2305a111873783;
RAM[37] = 64'h8082fed59be3fef5;
RAM[38] = 64'h8b85104727836749;
RAM[39] = 64'ha02367c98082dfed;
RAM[40] = 64'h00000000808210a7;
RAM[27] = 64'h4089093394be2004;
RAM[28] = 64'h04138522008905b3;
RAM[29] = 64'h19e3014000ef2004;
RAM[30] = 64'h64a2644260e2fe94;
RAM[31] = 64'h6749808261056902;
RAM[32] = 64'hdfed8b8510472783;
RAM[33] = 64'h2423479110a73823;
RAM[34] = 64'h10472783674910f7;
RAM[35] = 64'h20058693ffed8b89;
RAM[36] = 64'h05a1118737836749;
RAM[37] = 64'hfed59be3fef5bc23;
RAM[38] = 64'h1047278367498082;
RAM[39] = 64'h67c98082dfed8b85;
RAM[40] = 64'h0000808210a7a023;
end