27 Commits

Author	SHA1	Message	Date
Harshini Srinath	6aba0187d7	Update csr.sv ... Program clean up	2023-06-13 21:12:49 -07:00
Harshini Srinath	a2645dd576	Update csr.sv ... Program clean up	2023-06-12 18:51:37 -07:00
Ross Thompson	a963f0af3a	Updated source code to be compatible with verilator 5.011 for lint only.	2023-05-31 10:44:23 -05:00
Ross Thompson	8cf38b28aa	The privileged unit is parameterized using Lim's method.	2023-05-26 12:03:46 -05:00
David Harris	a5087818ba	Commented about Sstvecd trap vector alignment	2023-04-24 12:20:33 -07:00
David Harris	fd0c9e973d	Coverage improvements in ieu, hazard units	2023-03-31 08:33:46 -07:00
David Harris	da53f240d3	Refactored InstrValidNotFlushed into CSR Write signals	2023-03-30 17:06:09 -07:00
David Harris	406bb22b6a	Started factoring out InstrValidNotFlushed from CSRs	2023-03-30 14:56:19 -07:00
David Harris	9d8f9e4428	Reduced number of bits in mcause and medeleg registers	2023-03-29 07:02:09 -07:00
Ross Thompson	46b1bca4fc	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
David Harris	e03a533775	Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault	2023-03-22 06:29:30 -07:00
David Harris	a1eccf37dc	Fix Issue 145	2023-03-22 04:33:14 -07:00
David Harris	4cde207958	Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.	2023-03-18 10:10:58 -07:00
David Harris	6922298f21	Replaced FenceM with InvalidateICacheM for event counting of fence.i	2023-03-18 09:24:31 -07:00
Ross Thompson	4db17cde2f	Updated testbench to record coremark performance counters. ... Added comment about mtval probably not being correct for compressed instructions.	2023-03-08 17:11:27 -06:00
Ross Thompson	0cb5369351	Renamed BTB misprediction to BTA.	2023-03-03 00:18:34 -06:00
Ross Thompson	5b5677ccb8	Added divide cycle counter.	2023-03-02 23:59:52 -06:00
Ross Thompson	aabb454d1c	Added the i and d cache cycle counters.	2023-03-02 23:54:56 -06:00
Ross Thompson	cfca77172e	Added fence counter.	2023-03-02 23:29:20 -06:00
Ross Thompson	f32f8c109a	Added csr write counter, sfence vma counter, interrupt counter, and exception counter.	2023-03-02 23:21:29 -06:00
Ross Thompson	a313b10912	Added store stall to performance counters.	2023-03-02 23:10:54 -06:00
Ross Thompson	b98e007a53	Cleaned up branch predictor performance counters.	2023-03-01 17:05:42 -06:00
Ross Thompson	a6917d07f3	Name cleanup.	2023-02-28 17:48:58 -06:00
Ross Thompson	2ebe600f54	Name changes to reflect diagrams.	2023-02-28 15:37:25 -06:00
Ross Thompson	8bd4a4c35b	Renamed signals to match new figures.	2023-02-24 19:51:47 -06:00
David Harris	5b370bdc0f	Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.	2023-02-16 07:37:12 -08:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00