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Author SHA1 Message Date
David Harris
97ee3732fe Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-03 08:36:11 -08:00
David Harris
4dca69f205 Updated division radix test script with paths, but script is out of date for files it manipulates 2023-02-03 08:36:03 -08:00
Kevin Kim
3d67e48bef Merge branch 'main' of https://github.com/kipmacsaigoren/cvw 2023-02-03 16:00:36 +00:00
Kevin Kim
d47a44a62f ALU changes (ZBB) 
- handles inverted operand instructions
- handles shift-and-add instructions
 2023-02-03 16:00:32 +00:00
David Harris
1763de52ea Merge pull request #54 from ross144/main 
Fixed issue #50, itlb and dcache flush interlock
 2023-02-03 06:30:30 -08:00
Ross Thompson
4547da80ea Fixed bug #49. 
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
 2023-02-03 00:39:26 -06:00
Ross Thompson
659b511616 Lee Moore found another bug using imperas. 
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
 2023-02-02 23:52:21 -06:00
Kevin Kim
a0adcf6a85 Merge branch 'openhwgroup:main' into main 2023-02-02 21:41:55 -08:00
Kevin Kim
f0730c13e2 Started Zbb 
-Performs byte instructions (orc.b, rev8 (32/64))
 2023-02-03 05:40:38 +00:00
Kevin Kim
a0ea436b9c zbs minor lint fix 2023-02-03 05:31:50 +00:00
Kevin Kim
44e5a7e913 zbc initial done; passes lint. 
clmul logic changes have not verified yet
 2023-02-03 04:48:23 +00:00
David Harris
644dfe7463 Removed lab1matrix solutions 2023-02-02 19:40:41 -08:00
Kevin Kim
adc96ecaaa added bit reverse module, passes lint 2023-02-02 23:10:57 +00:00
David Harris
e6bfcd14fa Merged with memories 2023-02-02 14:50:46 -08:00
David Harris
80f42a8638 Renamed regression to sim 2023-02-02 14:48:23 -08:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
David Harris
3531afa5cf Update README.md 2023-02-02 12:59:28 -08:00
Kevin Kim
e2228f6341 started zbc 2023-02-02 20:11:11 +00:00
Kevin Kim
aadc1de746 zbs passes lint 2023-02-02 20:04:38 +00:00
James E. Stine
4b2a13bc44 Merge pull request #52 from stineje/main 
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
 2023-02-02 13:55:17 -06:00
James Stine
924e55325c Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22 2023-02-02 13:54:25 -06:00
Kevin Kim
ae5d7844a9 clmul finished initial hdl; passes lint 2023-02-02 19:49:14 +00:00
David Harris
e4f2e96449 Merge pull request #51 from stineje/main 
Modify generic/mem for rv32gc ram2
 2023-02-02 11:41:32 -08:00
James Stine
9a5023a17e Modify generic/mem for rv32gc ram2 2023-02-02 13:28:18 -06:00
Kevin Kim
f07ffbb63b continued clmul unit 2023-02-02 18:54:33 +00:00
David Harris
30ba42d498 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-02 10:28:40 -08:00
Kevin Kim
bd8f0189ee started clmul 2023-02-02 16:40:58 +00:00
David Harris
0af2ff969c Merge pull request #48 from ross144/main 
Fixed bug #47, ecall and ebreak don't commit
 2023-02-02 06:58:07 -08:00
Ross Thompson
3c8f07ffa1 Merge branch 'main' of github.com:ross144/cvw 2023-02-02 08:52:48 -06:00
Ross Thompson
3838ab232b Fixed bug #47 discovered by Lee Moore. 
ECALL and EBREAK do not commit their results.
 2023-02-02 08:52:06 -06:00
Ross Thompson
7f207527ce Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-02 08:48:19 -06:00
Kip Macsai-Goren
0281330fe8 Merge remote-tracking branch 'upstream/main' into main 2023-02-01 21:31:57 -08:00
Kip Macsai-Goren
f126d1e0ef added beginning of a ZBS instruction module to the ALU. Control signals still needed 2023-02-01 21:31:25 -08:00
Ross Thompson
279c62c402 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-01 19:24:10 -06:00
David Harris
0a540495f6 Removed O2 from fir Makefile to be consistent with lab. 2023-02-01 15:43:52 -08:00
David Harris
c5578cc2fb Merge pull request #45 from stineje/main 
Update ram2 and other memories and associated wrappers
 2023-02-01 15:06:30 -08:00
James Stine
fc5692629a Update ram2 and other memories and associated wrappers 2023-02-01 17:03:48 -06:00
Ross Thompson
3276353b8c Minor branch predictor bug fix. 2023-02-01 10:59:38 -06:00
Ross Thompson
51a2a71410 Removed unused signal. 2023-02-01 10:27:58 -06:00
David Harris
8601f04397 Fixed typo in DC setup for memories 2023-02-01 05:49:30 -08:00
David Harris
e820d1938a Only add memory libraries when targeting 28nm 2023-02-01 05:06:56 -08:00
David Harris
733b877f1d Merge pull request #36 from davidharrishmc/dev 
RV32imc configuration
 2023-02-01 04:44:36 -08:00
David Harris
ce82d8d550 Fixed merge conflict to get synthesis working again 2023-02-01 04:43:57 -08:00
David Harris
39942bbc45 Merge pull request #43 from mmasserfrye/main 
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
 2023-02-01 04:13:37 -08:00
Ross Thompson
6fb624950e Minor change to btb. 2023-02-01 00:24:54 -06:00
Madeleine Masser-Frye
57b35c293d added memories (not tested) 2023-02-01 06:08:27 +00:00
Ross Thompson
241d63ce1f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-01 00:01:14 -06:00
Madeleine Masser-Frye
a81d569e1a increased bpred size to (2^) 5 2023-02-01 05:51:31 +00:00
Madeleine Masser-Frye
d734f7af92 updated synth makefile to change all relevant 
ram ranges to 1FF
 2023-02-01 05:40:35 +00:00
Madeleine Masser-Frye
fa9a99c8e8 Merge branch 'main' of https://github.com/mmasserfrye/cvw 2023-02-01 05:23:04 +00:00