8 Commits

Author	SHA1	Message	Date
Ross Thompson	fc22e807e2	Merged testbench-fpga into testbench. ... Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.	2022-08-24 17:52:25 -05:00
David Harris	5ae88dbef0	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
Ross Thompson	64846c800e	Constraint changes for 40Mhz wally.	2022-04-04 10:50:48 -05:00
Ross Thompson	d83db2cde5	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	913a78323c	moved proposed-sdc	2022-01-07 12:44:21 +00:00
David Harris	d17a305538	Finished removing generate statements	2022-01-05 16:41:17 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00