114 Commits

Author	SHA1	Message	Date
Ross Thompson	41258529f0	Fixed bug in the top level of fpga verilog.	2021-12-03 17:55:36 -06:00
Ross Thompson	cb744280c3	Fixed a bunch of fpga issues.	2021-12-03 17:47:54 -06:00
Ross Thompson	35dd1b5c9f	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
Ross Thompson	5d4051d1c2	Constraints for fpga are still wrong.	2021-12-02 14:23:21 -06:00
Ross Thompson	2cfbdb1c47	Added tcl commands to build the implementation.	2021-12-02 10:17:30 -06:00
Ross Thompson	2a7467c76d	Separated timing constraints from ILA.	2021-12-01 18:15:04 -06:00
Ross Thompson	6a228ade04	Got fpga synthesis running from scripts.	2021-12-01 16:59:04 -06:00
Ross Thompson	96926877c4	Created top level FPGA module which replicates the schematic of the initial fpga design.	2021-11-30 17:18:28 -06:00
Ross Thompson	7f52d86980	Added make clean to fpga IP generator.	2021-11-29 18:42:28 -06:00
Ross Thompson	1117b90f40	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00
Ross Thompson	84116a756e	Added final IP generator script (proc_sys_reset).	2021-11-29 17:43:47 -06:00
Ross Thompson	ce91732856	Added ddr4 generator script.	2021-11-29 15:56:57 -06:00
Ross Thompson	9a0bf54840	Created tcl scripts to build 2 of the 4 xilinx IP.	2021-11-29 11:26:08 -06:00
Ross Thompson	2e0dcaaff9	Fpga simualtion files.	2021-10-11 10:24:40 -05:00