Ross Thompson
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525c7120b4
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Rename of dcache interface signals.
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2021-12-29 21:26:15 -06:00 |
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Ross Thompson
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995cfb1cf3
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Cleaned up some names in dcache and lsu.
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2021-12-29 11:21:44 -06:00 |
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Ross Thompson
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bc6e776609
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Converted mux4 to mux3 in dcache.
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2021-12-29 10:58:02 -06:00 |
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Ross Thompson
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15f1627a31
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Fixed interrupt delay bug by reverting CommittedM changes.
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2021-12-28 22:27:12 -06:00 |
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Ross Thompson
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a966764d88
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Removed CommittedM as it is redundant with LSUStall.
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2021-12-28 16:14:10 -06:00 |
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Ross Thompson
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b4ab435bff
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Major cleanup of the LSU.
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2021-12-28 13:10:45 -06:00 |
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Ross Thompson
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77e8ba619e
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Minor dcache cleanup.
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2021-12-28 11:29:16 -06:00 |
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Ross Thompson
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44b63fc0ba
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First cut at moving the dcache bus interface into the LSU.
Regression test does not run and there is a lot of cleanup to do.
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2021-12-27 18:12:59 -06:00 |
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Ross Thompson
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50e4463a7f
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It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
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2021-12-21 15:59:56 -06:00 |
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Ross Thompson
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9c2fc30507
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Signal renames.
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2021-12-19 22:21:03 -06:00 |
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Ross Thompson
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30770db4ac
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Removed lsuArb and placed remaining logic in lsu.sv.
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
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2021-12-19 21:34:40 -06:00 |
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Ross Thompson
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04d0b85f96
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Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
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2021-12-19 16:12:31 -06:00 |
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Ross Thompson
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fdf493bd47
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minro change. comments about needed changes in dcache.
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2021-12-19 13:53:02 -06:00 |
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Ross Thompson
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7d00649b61
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Formating changes to cache fsms.
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2021-12-13 17:16:13 -06:00 |
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Ross Thompson
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cd59809e42
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Fixed numerous errors in the preformance counter updates.
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
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2021-12-09 11:44:12 -06:00 |
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Ross Thompson
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e43aa6ead4
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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Ross Thompson
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2f85ac7f38
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Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
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2021-11-20 22:35:47 -06:00 |
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Ross Thompson
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d98baf90a3
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Replaced async reset flip flops with sync reset flip flops in cache and bpread.
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2021-10-27 09:57:11 -05:00 |
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Ross Thompson
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09dc3e1143
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Merge branch 'main' into fpga
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2021-10-20 16:24:55 -05:00 |
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Ross Thompson
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f4e64c2eaf
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Added debug signals to dcache.
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2021-10-20 15:52:05 -05:00 |
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David Harris
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df0b65e483
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replaced flopenl with flopenr when clearing to 0
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2021-10-18 16:53:18 -07:00 |
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Ross Thompson
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d09b381183
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Fixed the amo on dcache miss cpu stall issue.
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2021-09-17 22:15:03 -05:00 |
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Ross Thompson
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b92070a67a
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Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
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2021-09-17 10:25:21 -05:00 |
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Ross Thompson
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d4398c23fb
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Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
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2021-09-16 18:32:29 -05:00 |
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Ross Thompson
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4ca0c0ea7d
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Added flush controls to cachway.
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2021-09-16 16:56:48 -05:00 |
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Ross Thompson
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3ff8d0095d
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Fixed dcache to prevent latches in FPGA synthesized design.
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2021-09-11 12:03:48 -05:00 |
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Ross Thompson
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939ff663a5
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Forgot to include a few files in the last few commits.
Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
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2021-08-25 22:30:05 -05:00 |
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