David Harris
1ced158596
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
David Harris
98fa3a78dd
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
David Harris
376ca68cbb
Improved NAPOT test coverage
2023-08-30 21:04:36 -07:00
David Harris
c27ec6830d
Initial TLB NAPOT tests
2023-08-29 12:39:24 -07:00
David Harris
d12be1faac
Merge pull request #394 from harshinisrinath1001/main
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Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
49014e61bc
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
David Harris
fa49117521
Merge pull request #381 from harshinisrinath1001/main
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Tried to improve coverage of CSRI with priv.S
2023-08-21 13:28:39 -07:00
harshinisrinath
37bfb5998f
cleared stimer interrupt
2023-08-20 15:42:27 -07:00
harshinisrinath
fce2023aa8
tried to improve testing of csri in privileged module
2023-08-20 15:40:02 -07:00
David Harris
36a825c43b
Improved CSRU coverage with priv.S
2023-08-20 12:49:31 -07:00
harshinisrinath
2c2c117201
wrote testcase to write into FSCR
2023-08-20 12:10:08 -07:00
harshinisrinath
15dbbef9ad
Fixed bug and tried to reset menvcfg to improve testing of csri in priv.
2023-07-30 16:40:06 -07:00
harshinisrinath
dc6633c796
Improved testing of pmd in priv.
2023-06-16 17:13:54 -07:00
harshinisrinath
c9695e6813
Improve test coverage on ieu fw.
2023-06-16 16:09:48 -07:00
David Harris
9373ad3811
Fixed WALLY-trap test case to use menvcfg
2023-06-09 15:24:26 -07:00
James Stine
736ae7d749
Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing
2023-06-05 11:03:59 -05:00
Kevin Thomas
968c228fcc
Comment tlbGBL more discriptively
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Reduce redundant instructions
2023-05-04 19:13:47 -05:00
David Harris
2b9b2f21df
Merge branch 'main' into main
2023-04-28 07:51:32 -07:00
Liam Chalk
8ef9e77e00
Merge branch 'main' into main
2023-04-27 21:49:01 -07:00
Kevin Wan
c0cbd0fd2a
added tests for pmppriority module
2023-04-27 16:12:43 -07:00
David Harris
c04f636952
Update tlbASID.S
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fixed comment about restoring ASID to 0
2023-04-27 14:32:57 -07:00
Noah Limpert
26cb639f89
complete camline coverage on IFU and LSU
2023-04-27 14:26:10 -07:00
Liam
6803347a49
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
Alexa Wright
667c54c129
Merge branch 'openhwgroup:main' into main
2023-04-26 16:26:30 -07:00
Alexa Wright
55a74fd315
Excluded and added coverage for WFI test case.
2023-04-25 17:06:57 -07:00
Liam
309a56b8f8
pmpaddr0 and pmpaddr2 test cases
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Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
2023-04-25 15:37:04 -07:00
David Harris
8be5ed9b67
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
Liam
2ed9384238
pmpcfg test cases
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Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
2023-04-21 20:43:37 -07:00
Noah Limpert
cf150a2ea9
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
73cca666bf
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
Liam
2684a81754
Add pmpcfg test cases increasing IFU coverage
2023-04-19 11:58:22 -07:00
David Harris
79dbfae4af
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
59d153ace0
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
Alec Vercruysse
3de03abd9d
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
Liam
777028e43b
Add test cases for pmpcfg.S
2023-04-18 23:06:52 -07:00
Kevin Wan
fe51108740
a
2023-04-18 22:09:50 -07:00
Kevin Wan
fed7681695
Merge branch 'main' of https://github.com/koooo142857/cvw into main
2023-04-18 21:55:06 -07:00
koooo142857
ea39b53c97
Merge branch 'openhwgroup:main' into main
2023-04-18 21:53:46 -07:00
Kevin Wan
20a0803f46
Completely covers all PMPCFG_ARRAY_REGW cases
2023-04-18 21:50:48 -07:00
Kevin Wan
3ef81f4e6a
PMPCFG_ARRAY_REGW cases
2023-04-18 18:43:50 -07:00
Miles Cook
5cfd0577d1
Increase of TLB coverage in IFU
2023-04-17 18:35:03 -07:00
Diego Herrera Vicioso
34dd481f93
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Dygore
92a0827d80
Added multiple tests to increase FPU coverage
2023-04-14 14:41:05 -05:00
Dylan
4c91bb3b76
Merge branch 'openhwgroup:main' into main
2023-04-14 00:36:57 -05:00
Dygore
23dbca3991
Added tests for full coverage of the FPU result sign module
2023-04-14 00:36:12 -05:00
Noah Limpert
30ed9c2b69
add back K. Box and M. Cook Lsu test
2023-04-13 17:50:18 -07:00
Noah Limpert
187c5b07c7
make pull request more clean
2023-04-13 17:44:09 -07:00
Noah Limpert
c76de00d60
Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways"
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This reverts commit 0fea40282a
2023-04-13 17:40:39 -07:00
Noah Limpert
4ab27b4f12
Revert "Test File for Pull Request, Attempt to fill all four ways"
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This reverts commit f770243689
2023-04-13 17:28:37 -07:00
