Alec Vercruysse 3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 ... This hits some conditional coverage in each cacheway. A cache store hit happens at the same time as a StoreAmoMisalignedFault.		2023-04-19 01:34:01 -07:00
..
csrwrites.S
dcache1.py	Cover CacheWay edge case: CacheDataMem we=1 while ce=0.	2023-04-19 01:34:01 -07:00
dcache1.S	Cover CacheWay edge case: CacheDataMem we=1 while ce=0.	2023-04-19 01:34:01 -07:00
dcache2.S	add D$ test case to trigger a FlushStage while SetDirtyWay=1	2023-04-19 01:34:01 -07:00
ebu.S
fpu.S	Added multiple tests to increase FPU coverage	2023-04-14 14:41:05 -05:00
ieu.S
ifu.S
ifuCamlineWrite.S	Increase of TLB coverage in IFU	2023-04-17 18:35:03 -07:00
lsu.S	add back K. Box and M. Cook Lsu test	2023-04-13 17:50:18 -07:00
Makefile
pmp.S
priv.S	Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc	2023-04-15 23:13:39 -07:00
tlbKP.S
vm64check.S
WALLY-init-lib.h