Github_Repos/cvw
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202 Commits

Author SHA1 Message Date
Ross Thompson
00c61fc5b3 Found the DDR3 memory is not ready when issuing the first store. 2023-04-17 19:33:13 -05:00
Ross Thompson
8bebc56b56 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. 2023-04-17 18:39:25 -05:00
Ross Thompson
8377ff8c51 Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. 2023-04-17 16:37:18 -05:00
Ross Thompson
96781e0b2a Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. 2023-04-17 16:00:02 -05:00
Ross Thompson
fad0366d26 Adding in the ILA to the arty a7. 2023-04-17 14:54:10 -05:00
Ross Thompson
0be81fdfc8 Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster. 2023-04-17 12:16:31 -05:00
Ross Thompson
a7a362f82e Finally got the arty a7 to build. 2023-04-17 11:54:22 -05:00
Ross Thompson
9070b4adf5 OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :( 2023-04-17 11:10:19 -05:00
Ross Thompson
5da5b76449 Fixed more issues with arty a7 constarints. 2023-04-16 13:25:02 -05:00
Ross Thompson
d2272c0620 Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
 2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7 Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure. 2023-04-14 18:02:16 -05:00
Ross Thompson
b5799c896e Finally fixed the ddr3 mig script to work correclty. 2023-04-14 11:41:51 -05:00
Ross Thompson
679dc7d73b Progress on arty a7 board. 2023-04-13 17:57:12 -05:00
Ross Thompson
1861ca8c86 Fixed more bugs in the ila debug constraints. 2023-04-11 14:32:53 -05:00
Ross Thompson
b015e736a0 Updated to help debut Jacob's crossbar woes. 2023-04-11 14:22:42 -05:00
Ross Thompson
c7104bebd3 Fixed sum bugs with arty a7 ila script. 2023-04-11 10:00:06 -05:00
Ross Thompson
6123efd5b2 Updates for arty a7. 2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03 Fixed syntax errors in arty7 top level. 2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
Ross Thompson
d2d528cf3c Finally building ddr3 xilinx ip from script. 2023-04-10 14:36:33 -05:00
Ross Thompson
5aa614858f Started putting together the arty a7 board package files. 2023-04-10 13:15:55 -05:00
Jacob Pease
2b9e5608a4 Build doesn't work. AXI Crossbar has problems. 2023-04-06 16:01:58 -05:00
Ross Thompson
b57566e632 Added Jacob's ILA script. 2023-04-06 15:32:36 -05:00
Ross Thompson
c8baffba7c Started constrains file for arty a7 fpga. 2023-03-24 20:38:13 -05:00
Ross Thompson
c10d98b1c8 Updated fpga constraints to remove critical warning. 2023-03-24 19:09:36 -05:00
Ross Thompson
78ab9f59af Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
Jacob Pease
303c997a69 Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore 2023-03-24 17:01:27 -05:00
Ross Thompson
fe163bbab3 Updated fpga ila script. 2023-03-06 13:14:48 -06:00
Jacob Pease
b2a5786cda Disabled old SD card and attached IOBUF's to new SD peripheral. 2023-02-28 12:20:46 -06:00
Jacob Pease
2822cb273c AXI Crossbar is working. Fixed address width in generator script. 2023-02-22 15:13:16 -06:00
Jacob Pease
5161fd25cc Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
Jacob Pease
c1e7526570 Fixed debug signal names. Builds on the fpga. Bug in the crossbar. 2023-02-16 17:33:21 -06:00
Ross Thompson
920bd40822 fpga constraints updates 2023-02-07 15:22:14 -06:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
Jacob Pease
cfe792a814 Flipped crossbar inputs and outputs to correctly place masters. 2023-01-27 14:57:36 -06:00
Jacob Pease
eb3c6754f8 Removed IOBUF's from sdc_controller. 2023-01-27 14:35:34 -06:00
Jacob Pease
536039ad86 Modified makefile. Added axi protocol converter IP. 2023-01-23 19:30:29 -06:00
Jacob Pease
185e58ddcb Created missing wires for axi interfaces in fpgaTop.v. 2023-01-23 19:02:01 -06:00
Jacob Pease
24d0b1c860 Added extra core signal to mark_debug.txt. Modified wally.tcl 2023-01-23 17:00:24 -06:00
Jacob Pease
204fb84708 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-23 12:41:02 -06:00
Ross Thompson
64eaaa670c More fixes for the debug2.xdc constraints. 2023-01-20 20:48:19 -06:00
Ross Thompson
ee4c78c7fa More fixes to fpga ila debugger. 2023-01-20 20:28:21 -06:00
Ross Thompson
3effeb42c3 Fixed fpga constraints. 2023-01-20 20:18:04 -06:00
Ross Thompson
442de3f5b7 Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Ross Thompson
a4822c9f54 Added license and comments to new script. 2023-01-20 19:50:33 -06:00
Ross Thompson
b709c224ab Updated ignore to exclude copied files. 2023-01-20 19:47:33 -06:00
Ross Thompson
e06237ad92 Removed mark_debug vivado directive from source code. 
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
 2023-01-20 19:43:18 -06:00
Ross Thompson
9d8fed1d35 Test commit. 2023-01-20 17:27:09 -06:00
Ross Thompson
b25b93df11 Repaired fpga debugger. 2023-01-20 15:26:52 -06:00
Ross Thompson
3e1a54e80a Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Jacob Pease
4af0633cee Added IOBUFs to SDCDat. Edited debug2.xdc. Dwidth converter error. 2023-01-19 16:57:43 -06:00
Jacob Pease
dcb30dcfb2 Fixed errors in uncore and included newsdc stuff in wally.tcl 2023-01-17 16:46:00 -06:00
Jacob Pease
3b7e721823 Fixed typos. Apparently `defube causes a weird vivado error. 2023-01-13 16:59:18 -06:00
Jacob Pease
47c46bc9b5 Added IPs to wally.tcl. 2023-01-13 14:36:23 -06:00
Jacob Pease
b63927b474 Connected the axi_sdc_controller with an axi crossbar. 
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
 2023-01-13 13:56:01 -06:00
Ross Thompson
6cf5a99b5d Updated constraints to remove DivBusyE. 2022-12-30 10:51:35 -06:00
Ross Thompson
967d892088 Updated fpga constraints. 2022-12-24 10:21:16 -06:00
Ross Thompson
a2de53aeeb Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
b7224cc5ba Updated fpga constraints. 2022-12-21 14:50:01 -06:00
Ross Thompson
e326c9972c Updated vcu118 piniout. 2022-12-18 14:00:10 -06:00
Ross Thompson
9eac190468 Updated fpga constraints 2022-12-15 16:45:55 -06:00
rachanaerra
4f042b0adb updated constraints file 2022-12-05 15:05:21 -06:00
Ross Thompson
55335d1db6 Updated top level fpga file. 2022-11-18 11:10:45 -06:00
Ross Thompson
8692bafd04 Updated fpga wave configuration. 2022-11-16 15:57:19 -06:00
Ross Thompson
3de5144ae4 Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
Ross Thompson
b812549f38 Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s). 
Increased CPU clock speed from 30 Mhz to 35 Mhz.
 2022-11-11 15:33:03 -06:00
Ross Thompson
ebfee753ca Updates to fpga constraints. 2022-11-09 13:52:36 -06:00
Ross Thompson
fd1ef82310 Fixed bug with fpga makefile. 2022-11-07 09:20:05 -06:00
Jacob Pease
ec0cede2f2 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
Ross Thompson
1510c2d92f Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
ae01c8e824 Forget to include updated xdc file. 2022-10-24 13:51:21 -05:00
Ross Thompson
a45e612008 Updated debug2.xdc for interlock fsm changes. 2022-10-19 17:34:47 -05:00
Ross Thompson
962ba5e4b8 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
8f18bb9243 Updated constraints file to work with alternate uart. 2022-10-04 17:35:44 -05:00
Ross Thompson
6250a65ede added new constraints for fpga. 2022-09-17 22:20:06 -05:00
Ross Thompson
bd37a5c6dc Fixed fpga debug constraints. 2022-09-03 17:36:29 -05:00
Ross Thompson
c7055a3ee2 update to fpga wave. 2022-09-02 15:54:54 -05:00
Ross Thompson
2aa5886769 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
559e093ab5 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
Ross Thompson
1e1646da90 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
76f8c991a2 Updated fpga debugger to latest RTL version. 2022-08-19 17:13:36 -05:00
Ross Thompson
5d5042cd49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-19 16:39:28 -05:00
Ross Thompson
882f174553 Modified debugger for updated rtl. 2022-06-04 14:39:55 -05:00
Ross Thompson
92a2ad02db Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Ross Thompson
099b0464dd Added more plic debugging signals. 2022-05-21 14:04:08 -05:00
Ross Thompson
3c30751470 Updated the fpga constraints. 2022-05-21 13:32:03 -05:00
Ross Thompson
b853c4ba47 Updated fpga debugger. 2022-05-17 23:04:01 -05:00
Ross Thompson
f206dc7adb Updated debugger constraints. 2022-05-09 10:19:25 -05:00
Ross Thompson
a5d4e39e7d Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
0bcfd9d666 Added another GPR to debugger. 2022-04-17 18:12:05 -05:00
Ross Thompson
7135364d1a Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
9685365d2e Added signals to ila. 2022-04-07 21:09:50 -05:00
Ross Thompson
54de15752e Added sp to ila. 2022-04-07 16:29:41 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
2376d66ec2 Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00