213 Commits

Author	SHA1	Message	Date
Ross Thompson	637d60b64c	Progress.	2022-08-30 14:17:00 -05:00
David Harris	7d4e85bf21	Separated out radix 2 and radix 4 stages into different modules	2022-08-29 04:26:14 -07:00
David Harris	2788022c22	renamed srt to fdivsqrt	2022-08-29 04:04:05 -07:00
David Harris	f2517f8290	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
David Harris	60b673cafd	Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus	2022-08-27 05:31:56 -07:00
David Harris	37f0b52520	Fixed address decoder hanging buildroot	2022-08-26 22:01:25 -07:00
Ross Thompson	3b612d6201	Possible fixes for earily messup of rv32ic and rv64ic configs.	2022-08-25 14:42:08 -05:00
Ross Thompson	b0aea77b20	Added generate around uncore.	2022-08-25 10:35:24 -05:00
Ross Thompson	01a7718471	Added generate around ebu.	2022-08-25 09:24:13 -05:00
Ross Thompson	d10edfa5e0	No longer need wally-pipelined-fpga.do.	2022-08-24 18:10:45 -05:00
Ross Thompson	fc22e807e2	Merged testbench-fpga into testbench. ... Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.	2022-08-24 17:52:25 -05:00
Ross Thompson	517c0f6c35	Changed signal names.	2022-08-17 16:12:04 -05:00
Katherine Parry	cb0c1b7488	radix-2 1 copy passes testfloat	2022-08-06 22:54:05 +00:00
David Harris	7e5b78f240	plic-s debug	2022-08-03 12:33:09 +00:00
Ross Thompson	413a9bf58b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
David Harris	257107f908	Partitioned fma into separate files	2022-08-01 18:07:38 +00:00
Ross Thompson	1ee613ae6c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-31 12:48:51 -05:00
David Harris	2d7f4b133c	More work toward riscof tests	2022-07-26 06:19:13 -07:00
David Harris	416f5edfe0	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
David Harris	7f7b3359b0	Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings	2022-07-25 20:50:38 +00:00
Ross Thompson	719b00e338	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
Ross Thompson	69d520a7eb	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Ross Thompson	f3cf46d633	Added more i-cache signals to wave file.	2022-07-24 00:24:13 -05:00
Ross Thompson	8193946996	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-23 08:41:59 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Daniel Torres	d0aaae26fe	fixed wally rv32e tests, updated regression makefile to new testflow	2022-07-22 17:09:46 -07:00
Katherine Parry	b3d932cd61	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
Katherine Parry	fbe8bb2298	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
Ross Thompson	8698799077	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Ross Thompson	a79e5e11f6	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
Katherine Parry	cce5fb8dfd	moved Ss to execute stage	2022-07-18 20:48:56 +00:00
Katherine Parry	7268b4b334	removed underflow from inexactct calculation	2022-07-18 17:51:18 +00:00
Katherine Parry	5cb9c9f319	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
Katherine Parry	2fe8b6e34c	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
Katherine Parry	3c1bea1104	removed warnings and took a mux out of the critical path	2022-07-12 18:32:17 -07:00
Katherine Parry	18d7fee541	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-12 22:37:20 +00:00
Katherine Parry	bea4ec078d	variable interations implemented in radix-4 divider	2022-07-11 18:30:21 -07:00
Katherine Parry	97e7e619d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
Katherine Parry	75a8cea4e4	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
slmnemo	261248538c	sim-buildroot-batch now runs wally-pipelined-batch ... with option buildroot buildroot-no-trace to boot linux from step 0	2022-07-06 18:06:43 -07:00
David Harris	1bf701d958	Added check to halt testbench on failing to find file	2022-07-05 02:28:59 +00:00
slmnemo	39831e3a40	./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000	2022-06-29 13:40:11 -07:00
Katherine Parry	a5fb60eb1a	radix-4 early termination working for special cases - not working completely	2022-06-27 20:43:55 +00:00
Katherine Parry	43882d5878	modified result select to account for x/inf	2022-06-24 21:23:15 +00:00
Katherine Parry	b16e55906a	div debug - accounted for 1 bit normalization in exponent calculation	2022-06-23 22:59:43 +00:00
Katherine Parry	a5fc6757a1	generate qsel4 in verilog	2022-06-23 21:38:04 +00:00
slmnemo	3a471ac7d6	Added wally32periph to regression	2022-06-23 14:37:18 -07:00
Katherine Parry	1612daa294	Testfloat running division - not passing	2022-06-23 00:07:34 +00:00
slmnemo	09a633d7d1	changed order of makefiles and fixed warnings when running makes	2022-06-21 16:10:18 -07:00
slmnemo	6ba3a7615c	added individual makes for arch and wally tests as well as memfiles to Makefile. run using make archtests/wallytests/memfiles	2022-06-21 15:54:24 -07:00