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459 Commits

Author SHA1 Message Date
Sydney Riley
6c1f9de8c2 Manual merge in the coverage64gc 2023-03-29 15:25:27 -07:00
Kip Macsai-Goren
414cd26a9d updated tests to reflect non-writeable bits of deleg 2023-03-29 15:24:00 -07:00
Sydney Riley
287df517b9 Corrected authorship for IFU.S tests file 2023-03-29 15:20:46 -07:00
Sydney Riley
ede13491ef Starting IFU tests including c.fld compressed instruction 2023-03-29 15:15:47 -07:00
Noah Limpert
0fea40282a instantiate 5 4KiB arrays, aim to thrash all 4 ways 2023-03-29 13:08:33 -07:00
Noah Limpert
0e08c4393d access of 4KiB spaced mem locations, aim to fill + evict a line of all 4 ways 2023-03-29 13:07:34 -07:00
David Harris
0e02378532 Turned on FS bit in fpu.S coverage test 2023-03-29 06:10:05 -07:00
Diego Herrera Vicioso
4fa2959e56 Added test coverage cases for writing to STVAL, SCAUSE, SEPC, and STIMECMP CSRs. 2023-03-28 22:48:17 -07:00
David Harris
7132271a83 Started adding fpu fctrl tests 2023-03-28 21:13:25 -07:00
David Harris
aa31b45d88 Fixed RV32 tests after PMP fix 2023-03-28 08:35:23 -07:00
David Harris
39d3bf8e8a Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests 2023-03-28 06:58:17 -07:00
David Harris
01113320f4 Set PMP to allow all user/supervisor accesses in WALLY-init-lib 2023-03-28 06:46:11 -07:00
David Harris
20ebf7e536 CSRS privileged coverage test 2023-03-28 04:37:56 -07:00
Kip Macsai-Goren
b856698ce2 Revert "added premilinary boundary ccrossing cases" 
This reverts commit 3ce82f93c0.
 2023-03-24 11:27:41 -07:00
Kip Macsai-Goren
e949d3dc4b ported fixes to 32 bit tests 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
f0027aef23 replaced inerrupt tests with allowed versions 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
3c6b856068 Added cause_s_soft_from_m_interrupt 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
3ce82f93c0 added premilinary boundary ccrossing cases 2023-03-24 11:22:39 -07:00
David Harris
59f948d47c Start of EBU coverage tests 2023-03-24 08:12:02 -07:00
David Harris
83e13cef46 100% IEU coverage 2023-03-23 17:25:27 -07:00
David Harris
f8ad1b3db8 Improved IEU and bitmanip test coverage 2023-03-23 14:24:41 -07:00
David Harris
99c471ccfe Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
David Harris
af55524d97 Coverage improvements 2023-03-23 09:06:05 -07:00
David Harris
3fb9d1fcd0 Merged bit manip 2023-03-23 06:55:29 -07:00
David Harris
9dd2bafd6d Added new tests from class 2023-03-23 06:38:00 -07:00
Kip Macsai-Goren
fb415c3f92 Merge branch 'bit-manip' of github.com:kipmacsaigoren/cvw into bit-manip 2023-03-22 14:11:58 -07:00
kipmacsaigoren
e49e587eb5
Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 13:25:06 -07:00
Kip Macsai-Goren
a62b92e2ef Removed unused ISA string from spike YAML 2023-03-22 13:23:52 -07:00
David Harris
c1adc09da0 Added coverage tests to regression coverage 2023-03-22 13:00:10 -07:00
David Harris
c7aa602b01 Makefile improvements 2023-03-22 11:17:17 -07:00
Kevin Kim
605f41cd55
Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 10:33:15 -07:00
David Harris
dd517cdf00 Building infrastructure for coverage directed tests 2023-03-22 04:37:13 -07:00
Kevin Kim
2e149f9a31 Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-21 11:20:05 -07:00
David Harris
ba13add417 Added badinstr test file 2023-03-21 06:57:03 -07:00
kipmacsaigoren
10e0935207
Merge branch 'openhwgroup:main' into bit-manip 2023-03-07 21:29:03 -08:00
Kip Macsai-Goren
5c3f5fe8c6 added in the CSR name for stimecmp(h) 2023-03-04 15:53:03 -08:00
Kip Macsai-Goren
4fa78a02b7 removed changes to counteren from stimecmp tests 2023-03-04 15:46:57 -08:00
Kip Macsai-Goren
da9627708e Added correct causing and handling of S time interrupts to test suite. 2023-03-04 15:04:17 -08:00
Kip Macsai-Goren
82611ba889 Manual attempt to merge with upstream changes 2023-02-22 19:42:30 -08:00
Kip Macsai-Goren
3b50909ab2 added extra commands to make dut run work with spike for bit manip tests 2023-02-21 15:26:47 -08:00
Kip Macsai-Goren
66833f15f2 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
David Harris
5ce476241b Debug test case updates 2023-02-21 09:33:36 -08:00
Kip Macsai-Goren
8d0a600b96 Merge remote-tracking branch 'upstream/main' into main 2023-02-19 16:37:18 -08:00
David Harris
fe0a893182 Renamed section 12.3 to 8.3 in MMU test definitions 2023-02-19 05:46:46 -08:00
Kip Macsai-Goren
883a6ca005 merge upstream synth changes 2023-02-18 14:35:19 -08:00
Kip Macsai-Goren
02bc03af42 fixed makefile for 32 bit arch tests, restored original make for all others 2023-02-17 09:57:56 -08:00
Kip Macsai-Goren
b943470049 Modified arch64 tests to remove floating point and double tests from hanging make 2023-02-17 09:51:55 -08:00
David Harris
4414173e7a Debug test case update 2023-02-15 06:42:38 -08:00
Kevin Kim
405bbcc6a4 added critical rsync command to python script and builds I-ext tests 
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
 2023-02-14 10:40:29 -08:00
Kevin Kim
6d4f1dd928 updated python script to generate bash file 2023-02-11 11:08:11 -08:00
Kevin Kim
8d28839d72 changed python file to use WALLY env variable 2023-02-11 00:30:56 +00:00
Kip Macsai-Goren
f9d934e5ae Added necessary files to make bit make and run bit manipulation tests as part of regression 2023-02-10 10:35:19 -08:00
David Harris
8ad5f2b181 Added RVTEST_CASE to testgen header 2023-02-09 18:25:24 -08:00
David Harris
51a792431f Moved test generators 2023-02-09 18:24:48 -08:00
David Harris
f2c7a489b2 Test gen header 2023-02-09 18:14:26 -08:00
David Harris
93637fd9cb debug simulating, produing discrepancy 2023-02-06 16:47:56 -08:00
David Harris
bb39570576 Fixed floating point crash in debug.S 2023-02-06 15:38:57 -08:00
David Harris
aba8b9a64b More progress on debug.S, but it crashes in Spike 2023-02-04 09:59:22 -08:00
David Harris
1bb5599806 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
0f7ea52f9b Started making debug testcase 2023-02-04 08:18:55 -08:00
David Harris
8078cafa27 Renamed regression to sim 2023-02-02 14:48:23 -08:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
David Harris
8b34f5ac98 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 18:18:53 -08:00
Kip Macsai-Goren
95b26c49b9 Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts. 2023-01-28 17:29:35 -08:00
David Harris
99f967b6f6 Modified testgen to not produce reference outputs 2023-01-27 07:25:40 -08:00
David Harris
71d1c8fc68 Removed unused WALLY test references 2023-01-27 07:25:04 -08:00
David Harris
ae7d23380a Removed unused reference files 2023-01-27 07:21:55 -08:00
David Harris
7839fe2402 Removed f tests from rv32e 2023-01-27 06:15:20 -08:00
David Harris
b2c8c37077 Update riscof makefile to use rv32gc config 2023-01-27 05:57:58 -08:00
David Harris
8362e7466f Renamed spike_rv32imc_isa.yaml to rv32gc to reflect cases tested 2023-01-27 05:56:49 -08:00
David Harris
58a973ec97 Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases 2023-01-23 05:00:11 -08:00
David Harris
3d13683c07 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Ross Thompson
6cbce9672d Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
0eda4b1ab3 core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
Ross Thompson
0eceeeeeaa Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
Kip Macsai-Goren
ffae1c5ee6 added fs=00 to status fp enabled test 2022-12-22 15:15:53 -08:00
Kip Macsai-Goren
a768d70093 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Kip Macsai-Goren
7aadf50f26 updated trap handler alignemnts to 64 bytes in priv tests 2022-12-22 14:23:04 -08:00
David Harris
c7f3aae084 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
Ross Thompson
c3b43b2fac Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
0b4186f1e8 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
David Harris
03c700d91c Restored rv32d arch test after new push 2022-12-20 10:56:33 -08:00
Ross Thompson
4f56e6ff5d I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
b4229c01ca Have a basic cache test to fill all ways and sets. 2022-12-18 17:20:30 -06:00
Ross Thompson
376b01fcb8 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
ebdac1a9d0 Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
David Harris
5f637ef4a7 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
Kip Macsai-Goren
2dfa426e10 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
1d268fded4 added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
7411d50a78 added all 32 bit tests to 64 bit periph tests except gpio 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
badc684f07 added copies of 64 bit tests to 32 bit periph and priv tests 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
282d06b45f added -01 to all WALLY tests 2022-12-05 20:16:02 -08:00
Ross Thompson
128b3d20e7 Updated riscv arch test removed misaligned1. 2022-12-04 00:18:10 +00:00
Kip Macsai-Goren
af00eadec2 added tests for invalid address being written to satp. Not passing regression 2022-11-27 13:22:35 -08:00
Kip Macsai-Goren
6fdd603ba1 added potential fix to overrun error and fifo interrupt error. test passes 2022-11-06 22:01:02 -08:00
Kip Macsai-Goren
b42fc7ec6d fixed fifo timout handling. error now in data ready interrupt 2022-11-05 13:34:24 -07:00
Kip Macsai-Goren
23268d22e5 fixed broken instructions so make works. 2022-11-03 23:06:20 +00:00
Ross Thompson
24cb36c38d Updated to put dtb into the rodata segment for our linker script. 2022-11-03 17:48:20 -05:00
Ross Thompson
041ab8e401 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-03 17:36:04 -05:00
Ross Thompson
34cfc01d1c Potentially a valid zero stage boot loader based on cva6. 2022-11-03 17:35:57 -05:00
Ross Thompson
f81d1e15b6 More outline for uart timeout interrupt. 2022-10-28 13:53:56 -05:00
Ross Thompson
372b9890ef Untested change to uart test for outline of how to handle rx fifo timeout. 2022-10-28 13:31:16 -05:00
Kip Macsai-Goren
d4dd2dcc08 Added test for UART FIFO timeout. Does not pass regression 2022-10-25 05:35:56 +00:00
Ross Thompson
ae7a71c0f4 Created one off test to replicate the floating point forwarding hazard bug. 2022-10-22 16:29:12 -05:00
Kip Macsai-Goren
d5cd67cf09 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
0d2fcaeab1 added xlen and endianness test edits. xlen passes but endinanness still won't make 2022-09-26 05:03:19 +00:00
Kip Macsai-Goren
3f4c825a1a added mstatus uxl, sxl bit tests (not tested in regression yet) 2022-09-18 00:11:29 +00:00
Kip Macsai-Goren
dda3b2d383 ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
Kip Macsai-Goren
99596fac84 Fixed typos in existing endianness test 2022-09-18 00:09:52 +00:00
Kip Macsai-Goren
657e19df08 added full coverage of subword loads and stores to endianness test 2022-09-17 23:14:38 +00:00
Kip Macsai-Goren
a4fc5d3476 Created initial endianness tests 2022-09-16 01:06:26 +00:00
David Harris
8b8f045491 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
62252c2167 Debugging plic-s test 2022-08-03 13:21:09 +00:00
David Harris
6ee8036ae7 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
e3ea86f984 Started plic-s tests 2022-08-03 03:48:08 +00:00
David Harris
d2de84a456 Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
763a6d7340 Fixed UART reference output 2022-07-27 22:16:38 +00:00
David Harris
f61f0645fe Finished UART test 2022-07-27 04:06:59 +00:00
David Harris
da275e3c26 Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
slmnemo
a32698811d Updated reference file for UART test 2022-07-26 09:39:31 -07:00
slmnemo
8141530f10 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-26 09:15:20 -07:00
slmnemo
528dfd9170 Committing changes made to UART test 2022-07-26 09:14:40 -07:00
David Harris
449c80b5f7 More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
539174f6f6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
David Harris
55ab81e37b More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
6b172723bd Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
slmnemo
5b71ceac5c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
0bfc3fda1b Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
b726b05d61 fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Daniel Torres
e02c67ed5e fixed 32priv tests, now passing 2022-07-22 15:35:20 -07:00
Daniel Torres
d95b266d49 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
2bbfd67082 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
840c40a7ab UART updates and PMA fix 2022-07-22 14:49:03 -07:00
slmnemo
6d8988f71f Added test comments to reference output 2022-07-22 12:35:59 -07:00
Daniel Torres
5d7171f6f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
526f70e772 commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
12c92a05ff Added new PLIC and UART tests 2022-07-22 07:12:55 -07:00
slmnemo
49565f944c Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
bd918d37ba added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
d44ec059d0 made makefile more specific, just incase future additions 2022-07-21 12:50:02 -07:00
Daniel Torres
6e9b4f4075 removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
slmnemo
77f7b179ee fixed GPIO test by adding a new function to clear PLIC interrupts 2022-07-19 08:59:16 -07:00
Daniel Torres
c65aa54a1e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-18 12:13:48 -07:00
Daniel Torres
3f5a5e1093 added the sail change to spike to let it all run normally 2022-07-18 12:13:15 -07:00
Katherine Parry
8506d2be4c fixed uncommented line in makefile 2022-07-14 00:01:07 +00:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
slmnemo
43549b10fb Fixed error in gpio test 2022-07-08 02:27:16 -07:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00