Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 05:24:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
4,984 Commits 4 Branches 2 Tags 52 MiB
61efb22db1
Commit Graph

4984 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Ross Thompson
61efb22db1 More fixes to fpga ila debugger. 2023-01-20 20:28:21 -06:00
Ross Thompson
e28ea2d630 Fixed fpga constraints. 2023-01-20 20:18:04 -06:00
Ross Thompson
0ed9811e31 Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Ross Thompson
4ccea17648 Added license and comments to new script. 2023-01-20 19:50:33 -06:00
Ross Thompson
9c83b2dff5 Updated ignore to exclude copied files. 2023-01-20 19:47:33 -06:00
Ross Thompson
25bd2e4670 Removed mark_debug vivado directive from source code. 
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
 2023-01-20 19:43:18 -06:00
Ross Thompson
07308e2c14 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
Ross Thompson
6ccb3a0147 Test commit. 2023-01-20 17:27:09 -06:00
David Harris
c2f7f7324d test 2023-01-20 15:23:38 -08:00
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
David Harris
1933ea39fa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-20 14:19:10 -08:00
David Harris
0f68fccf82 Started adding bit manipulation unit 2023-01-20 14:19:07 -08:00
Ross Thompson
11c6106022 Repaired fpga debugger. 2023-01-20 15:26:52 -06:00
Ross Thompson
3d71d0196c Updated figure cache references. 2023-01-20 15:01:54 -06:00
Ross Thompson
5b740fbf60 Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
b1f3bd566c Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
f78bfc4940 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
c7f4970597 Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
6142c96946 Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
7e96f3e8f7 Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
95de716a17 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
b8a699270e More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
032332ebae renamed comparator module 2023-01-20 10:13:47 -08:00
David Harris
1c07eb623d Updated HMC Synopysys license manager 2023-01-20 10:13:20 -08:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
4a2d02ab28 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
11c44006c4 Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
eb19b1b499 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
63dbebcb5a Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
91bd55d9ba ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
30935fd2b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
78e8598ec8 Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
Ross Thompson
f7b869960a Rough draft of Install guide. 2023-01-19 17:27:45 -06:00
David Harris
aed6f79d1e Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
ad3b528b5d Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
264362ce17 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
a1b25e1039 RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
75391f4b56 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
40d62ec0d1 Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
999477bb02 Formatting and name changes. 2023-01-19 14:16:29 -06:00
Ross Thompson
0bbf6e4ae2 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
21b2b10e78 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
db48e547f0 Formatting. 2023-01-18 19:11:30 -06:00
Ross Thompson
9170827c98 Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill. 2023-01-18 19:10:34 -06:00
Ross Thompson
e79c403fe1 More IROM cleanup. 2023-01-18 18:47:02 -06:00
Ross Thompson
63577cbf4a Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
2d945963e6 Added comments to decompress.sv. May want to consider additional documentation. 2023-01-18 18:26:51 -06:00
Ross Thompson
f34c67722d Formatted subword* and bytemask. 2023-01-18 18:20:22 -06:00
Ross Thompson
f288b9ca14 Formatting. 2023-01-18 18:17:48 -06:00
Ross Thompson
cc186d0f3b Formatting. 2023-01-18 18:16:56 -06:00