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Author	SHA1	Message	Date
Ross Thompson	5c49cc4dd0	Fixed bug with fpga makefile.	2022-11-07 09:20:05 -06:00
Ross Thompson	d4f4950d2c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-07 09:10:51 -06:00
Kip Macsai-Goren	21e045eb7d	added potential fix to overrun error and fifo interrupt error. test passes	2022-11-06 22:01:02 -08:00
cturek	d571b5f9a5	propagated otfc swap to Rad2 and 4 qslc	2022-11-06 23:32:38 +00:00
Ross Thompson	e7d24609cd	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-06 17:22:25 -06:00
cturek	54f09f3616	Added conditional OTFC swap for simplified int postprocessing	2022-11-06 23:09:09 +00:00
cturek	c3e635c788	Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv	2022-11-06 22:40:21 +00:00
cturek	a49ea2a16d	Added n and rightshiftx	2022-11-06 22:31:48 +00:00
cturek	350d4d254f	p calculation	2022-11-06 22:24:21 +00:00
cturek	83051a5351	Changed lzc names, started int/fp size merge in preproc	2022-11-06 22:21:35 +00:00
cturek	2cbe2fd70b	Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.	2022-11-06 22:08:18 +00:00
cturek	6bc4c1318e	Added new macros for int div preprocessing, added p, n, and rightshiftx logic	2022-11-06 21:53:48 +00:00
Kip Macsai-Goren	90ef371abc	fixed fifo timout handling. error now in data ready interrupt	2022-11-05 13:34:24 -07:00
David Harris	53a88fec8f	Reorder embench tests to prevent crash	2022-11-04 15:21:51 -07:00
David Harris	60cfa0d69c	HPTW cleanup	2022-11-04 15:21:09 -07:00
Ross Thompson	44ee31a7f6	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-04 13:30:08 -05:00
Kip Macsai-Goren	c06da6e6fe	fixed broken instructions so make works.	2022-11-03 23:06:20 +00:00
Ross Thompson	65feca8bed	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-03 17:48:35 -05:00
Ross Thompson	f1eb20ef4d	Updated to put dtb into the rodata segment for our linker script.	2022-11-03 17:48:20 -05:00
cturek	06a9305766	renamed remOp to RemOp	2022-11-03 22:37:25 +00:00
Ross Thompson	1d7002e5c5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-03 17:36:04 -05:00
Ross Thompson	ccce0df535	Potentially a valid zero stage boot loader based on cva6.	2022-11-03 17:35:57 -05:00
cturek	e37f564e84	Added rem/div operation to postprocessor	2022-11-02 17:49:40 +00:00
Ross Thompson	44171c342d	Reduced complexity of logic supressing cache operations.	2022-11-01 15:23:24 -05:00
cturek	e8d7607e87	Added buffered signals for int/fp	2022-10-28 21:47:24 +00:00
Ross Thompson	103514a8e0	More outline for uart timeout interrupt.	2022-10-28 13:53:56 -05:00
Ross Thompson	21eca47d2e	Untested change to uart test for outline of how to handle rx fifo timeout.	2022-10-28 13:31:16 -05:00
cturek	9f41e57f03	Config Cleanup	2022-10-27 22:38:56 +00:00
Ross Thompson	dc3a9f2342	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-10-26 14:48:50 -05:00
Ross Thompson	403434580d	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
cturek	7301fc7f18	small signal cleanup	2022-10-26 18:42:49 +00:00
cturek	6caf7bb7e2	abs for int inputs	2022-10-26 16:18:05 +00:00
cturek	ec4646b412	Added signed division to fdivsqrt	2022-10-26 16:13:41 +00:00
cturek	71d16eacef	unbroke DIVb	2022-10-26 16:11:51 +00:00
cturek	1febdb75b7	Config cleanup	2022-10-25 21:04:09 +00:00
Jacob Pease	160ca366c8	Added PLIC signals for debugging on FPGA.	2022-10-25 13:57:09 -05:00
cturek	ff7d6b2932	Started Integer Preprocessing	2022-10-25 17:48:43 +00:00
Kip Macsai-Goren	6e45698b86	Added test for UART FIFO timeout. Does not pass regression	2022-10-25 05:35:56 +00:00
Kip Macsai-Goren	7448ee5e84	added additional cache stats to coremark postprocess script	2022-10-25 02:56:25 +00:00
Kip Macsai-Goren	5eb331b65e	added I cache stats to coremark output	2022-10-25 02:55:32 +00:00
Ross Thompson	d58a862f59	Added new device trees for vcu118 and vcu108 boards.	2022-10-24 17:45:10 -05:00
Ross Thompson	9ba487c323	Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.	2022-10-24 15:38:39 -05:00
Ross Thompson	92ace4d8f7	Forget to include updated xdc file.	2022-10-24 13:51:21 -05:00
Ross Thompson	7244ca1e7b	Bit width error.	2022-10-24 13:48:47 -05:00
Ross Thompson	048ed01554	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-10-24 10:12:39 -05:00
Ross Thompson	51408c620e	Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.	2022-10-23 13:46:50 -05:00
Ross Thompson	775309165b	Small cleanup of interlockfsm.	2022-10-22 16:29:51 -05:00
Ross Thompson	a59df0c77d	Created one off test to replicate the floating point forwarding hazard bug.	2022-10-22 16:29:12 -05:00
Ross Thompson	6696624971	comment updates.	2022-10-22 16:28:44 -05:00
Ross Thompson	12c5525807	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-10-22 16:27:30 -05:00