28 Commits

Author	SHA1	Message	Date
bbracker	612f7a9ee4	added a delay to sel signals	2021-03-05 15:07:34 -05:00
bbracker	a1223ee13b	more merging fixes	2021-03-05 14:36:07 -05:00
bbracker	2cd0f19129	remove deprecated mem signals	2021-03-05 14:27:38 -05:00
bbracker	62dd9e3075	first merge of ahb fix	2021-03-05 14:24:22 -05:00
Noah Boorstin	cfcd7d1518	busybear: make imperas tests work again	2021-03-04 22:44:49 +00:00
Noah Boorstin	5c456e2d7f	busybear: comment out instraccessfaultf for imem for now	2021-03-04 20:26:41 +00:00
Noah Boorstin	fde94f9057	Merge branch 'main' into busybear ... Conflicts: wally-pipelined/src/uncore/imem.sv	2021-03-04 20:16:03 +00:00
Teo Ene	b15ef47d24	Fix to 32-bit option of commit 2d40898158	2021-03-04 01:33:34 -06:00
Noah Boorstin	923489fe16	busybear: probably discovered bug in ahb code	2021-03-01 20:56:04 +00:00
Noah Boorstin	b3247eadd2	busybear: more adapting to new memory system	2021-03-01 18:50:42 +00:00
Noah Boorstin	f11b3108d8	busybear: fix bootram range	2021-03-01 17:45:21 +00:00
Teo Ene	2d40898158	Properly implemented the fix from commit 5fee65231e	2021-02-28 22:22:04 -06:00
Noah Boorstin	17715085ba	busybear: start preloading bootmem	2021-02-28 20:43:57 +00:00
Noah Boorstin	2769b147cb	busybear: add 2nd dtim for bootram	2021-02-28 16:08:54 +00:00
Noah Boorstin	969c094489	busybear: remove gpio, start adding 2nd ram	2021-02-28 06:02:40 +00:00
David Harris	0258901865	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	1b61d78ac2	Retimed peripherals for AHB interface	2021-02-26 00:55:41 -05:00
Teo Ene	a35fdac75b	Fixed previous commit	2021-02-25 11:24:44 -06:00
Teo Ene	5fee65231e	Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.	2021-02-25 11:23:01 -06:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
David Harris	f372e2b8e8	Debugging Bus interface	2021-02-22 13:48:30 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
bbracker	deb7780897	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	9f9c3bcece	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00