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482 Commits 4 Branches 2 Tags 53 MiB
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24 Commits

Author SHA1 Message Date
Noah Boorstin
4be19421c4 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
bbracker
eea7e2e47e first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Noah Boorstin
847bf0b9a6 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
a226e24ed3 busybear: update memory map, add GPIO 2021-03-18 12:17:35 -04:00
Noah Boorstin
162955de69 busybear: add COUNTERS define 2021-03-16 21:08:47 -04:00
Shreya Sanghai
d9b1e7d67f added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Shreya Sanghai
a79e26f9d8 added global history branch predictor 2021-03-16 16:06:40 -04:00
Ross Thompson
8e51935082 Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Thomas Fleming
e57b6cf18c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
Ross Thompson
d6bc34121f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
ca2a65770c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Thomas Fleming
85dcbee86b Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Noah Boorstin
0af002eb2f busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Noah Boorstin
f11b3108d8 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
Noah Boorstin
2769b147cb busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489 busybear: remove gpio, start adding 2nd ram 2021-02-28 06:02:40 +00:00
Noah Boorstin
cca60ed06d update busybear testbench to conform to new structure 
aaaaaaaaaaaaaaaaaahhhh so many changes

also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
 2021-01-30 19:19:00 +00:00
Noah Boorstin
7183910c84 update busybear testbench to conform to new structure 2021-01-29 17:46:50 +00:00
Noah Boorstin
0fa7cffb11 busybear: lie about MISA to match OVP's MISA 2021-01-29 00:58:56 -05:00
Noah Boorstin
91dcffa26f Update busybear tests to conform to new directory structure 2021-01-25 20:37:18 -05:00
David Harris
bf07ec92b5 Added test configurations 2021-01-25 11:28:43 -05:00