Jacob Pease
8b97d323e0
Fixed GPIO pin names in fpgaTop.v
2023-07-25 20:57:04 -05:00
Ross Thompson
3eeecd2f27
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
36785848a5
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
bae5359c6b
Fixed typo in fpga top for arty a7.
2023-07-19 11:37:29 -05:00
Jacob Pease
142ec857ed
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Ross Thompson
4bee446cad
Vivado requires an intermediate wrapper file for parameterization.
2023-06-16 16:30:14 -05:00
Ross Thompson
2f35bec970
FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
2023-06-16 15:40:13 -05:00
Jacob Pease
2ad9c72acc
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Jacob Pease
53de2bf782
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Jacob Pease
2b9e5608a4
Build doesn't work. AXI Crossbar has problems.
2023-04-06 16:01:58 -05:00
Ross Thompson
78ab9f59af
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
Jacob Pease
303c997a69
Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore
2023-03-24 17:01:27 -05:00
Jacob Pease
b2a5786cda
Disabled old SD card and attached IOBUF's to new SD peripheral.
2023-02-28 12:20:46 -06:00
Jacob Pease
2822cb273c
AXI Crossbar is working. Fixed address width in generator script.
2023-02-22 15:13:16 -06:00
Jacob Pease
cfe792a814
Flipped crossbar inputs and outputs to correctly place masters.
2023-01-27 14:57:36 -06:00
Jacob Pease
eb3c6754f8
Removed IOBUF's from sdc_controller.
2023-01-27 14:35:34 -06:00
Jacob Pease
185e58ddcb
Created missing wires for axi interfaces in fpgaTop.v.
2023-01-23 19:02:01 -06:00
Jacob Pease
4af0633cee
Added IOBUFs to SDCDat. Edited debug2.xdc. Dwidth converter error.
2023-01-19 16:57:43 -06:00
Jacob Pease
dcb30dcfb2
Fixed errors in uncore and included newsdc stuff in wally.tcl
2023-01-17 16:46:00 -06:00
Jacob Pease
3b7e721823
Fixed typos. Apparently `defube causes a weird vivado error.
2023-01-13 16:59:18 -06:00
Jacob Pease
47c46bc9b5
Added IPs to wally.tcl.
2023-01-13 14:36:23 -06:00
Jacob Pease
b63927b474
Connected the axi_sdc_controller with an axi crossbar.
...
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
2023-01-13 13:56:01 -06:00
Ross Thompson
55335d1db6
Updated top level fpga file.
2022-11-18 11:10:45 -06:00
Ross Thompson
6250a65ede
added new constraints for fpga.
2022-09-17 22:20:06 -05:00
Ross Thompson
29743c5e9e
Fixed two issues.
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First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
955ddcfbe1
Fixed bug in the top level of fpga verilog.
2021-12-03 17:55:36 -06:00
Ross Thompson
e94fb2aaec
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
Ross Thompson
5ea9ec0ae6
Created top level FPGA module which replicates the schematic of the initial fpga design.
2021-11-30 17:18:28 -06:00
