131 Commits

Author	SHA1	Message	Date
Ross Thompson	f604a0d79e	cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.	2022-01-05 22:56:18 -06:00
Ross Thompson	a4afc1bc54	More name cleanup in cache.	2022-01-05 22:37:53 -06:00
Ross Thompson	e74e8c2e86	Changed names of address in caches. ... Removed old cache files.	2022-01-05 22:19:36 -06:00
Ross Thompson	1ab3a17ff7	Updates to support fpga.	2022-01-05 18:07:23 -06:00
Ross Thompson	9ea34e390a	Fixed xilinx synth error with $error in extend.sv	2022-01-05 17:48:08 -06:00
Ross Thompson	de32930e63	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-05 16:57:29 -06:00
Ross Thompson	da585b30f9	Slower but correct implementation of flush.	2022-01-05 16:57:22 -06:00
David Harris	fed44cf9cf	Reinstated many arch f/d tests that had failed because of memfile issues	2022-01-05 22:44:10 +00:00
David Harris	8305eb80ff	Restored many of the arch32f and arch64d that had been failing because of memfile issues	2022-01-05 22:23:46 +00:00
David Harris	90dd961ea5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-05 22:10:33 +00:00
David Harris	07932ad0aa	Replaced exe2memfile with SiFive elf2hex	2022-01-05 22:10:26 +00:00
Ross Thompson	0310df96a4	Changes to wave file.	2022-01-05 14:16:59 -06:00
Ross Thompson	7086a0ed08	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-05 14:15:27 -06:00
Ross Thompson	cc51a27a34	Fixed bug with flush dirty not cleared in the correct cache line.	2022-01-05 14:14:01 -06:00
David Harris	d17a305538	Finished removing generate statements	2022-01-05 16:41:17 +00:00
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	da5ead23bf	Removed more generate statements	2022-01-05 16:01:03 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
Ross Thompson	98be8201b2	Renamed most signals inside cache.sv so they are agnostic to i or d.	2022-01-04 23:52:42 -06:00
Ross Thompson	fffaf654e6	the i and d caches now share common verilog.	2022-01-04 23:40:37 -06:00
Ross Thompson	13dbf3cc0f	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
Ross Thompson	cb301a78ad	Fixed bug where last line of dcache was not written back to memory on dcache flush.	2022-01-04 21:55:48 -06:00
Ross Thompson	101a8bdb5b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-04 18:41:52 -06:00
Ross Thompson	ecc7bf5237	Fixed dcache flush.	2022-01-04 18:40:58 -06:00
David Harris	9ddc6db0a6	Removed imperas mmu tests; using wallypriv instead	2022-01-04 23:14:53 +00:00
Kip Macsai-Goren	c65fc4d5e6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 21:30:51 +00:00
Kip Macsai-Goren	46b0cb810d	fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh.	2022-01-04 21:30:38 +00:00
David Harris	0a7ec3e58d	Fixed bad address for F/fmsub_b18-01	2022-01-04 21:04:06 +00:00
David Harris	d1a7416028	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-04 19:47:51 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00