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491 Commits

Author SHA1 Message Date
Limnanthes Serafini
5d12afa671 Some cleanup 2023-04-13 21:01:57 -07:00
David Harris
b378001213
Merge pull request #237 from SydRiley/main 
fctrl coverage at 100% after removing redundancies from conditionals
 2023-04-13 17:10:46 -07:00
Limnanthes Serafini
e33721fbe4 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
c427b4c896 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Sydeny
1dab409bae Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Sydeny
e2520c8a27 fctrl coverage at 100% after removing redundancies from conditional statements 2023-04-12 13:07:30 -07:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
David Harris
44023e7ee7 Removed unnecessary start term from initialization muxes to simplify and improve coverage 2023-04-12 03:34:01 -07:00
David Harris
28c02a7e6a Fixed fdivsqrt to avoid going from done to busy without going through idle first 2023-04-12 02:48:40 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Limnanthes Serafini
fdb81e44c9 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Alexa Wright
34fd402f23 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
Ross Thompson
132016f131 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
Kevin Thomas
640310cf94 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
David Harris
4a2f641348 Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
495f2ed274 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
David Harris
5119222c2f Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
7ad8d7f774 Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
c24e81c57f Division cleanup 2023-04-06 21:42:34 -07:00
David Harris
ce931d1fc5 Simplified integer division preprocessing in fdivsqrt 2023-04-06 16:43:28 -07:00
David Harris
1569bfbb98 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Ross Thompson
fe922c8fac Fixed syntax error. 2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1 Added note about strange vivado behavior not inferring block ram. 2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997 Similifed the no byte write enabled version of the sram model. 2023-04-06 14:18:41 -05:00
Kevin Thomas
1931859c45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-06 12:38:41 -05:00
David Harris
52dcd63d1e
Merge pull request #211 from ross144/main 
Fixes the issue introduced by the fix for issue 203
 2023-04-05 21:50:32 -07:00
Ross Thompson
1478115faf Fixed wally64/32priv test hangup. 
The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
 2023-04-05 23:13:45 -05:00
Kevin Thomas
e70a081924 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 17:43:43 -05:00
Ross Thompson
f2c26ff886
Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
Alec Vercruysse
2a3d9f8c89 Update ram1p1rwe (ce & we) coverage exlusion explanation 2023-04-05 14:54:58 -07:00
Kevin Thomas
c4a9bb4269 Formating white space 2023-04-05 15:30:55 -05:00
Kevin Thomas
7345927cb1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:04:12 -05:00
Ross Thompson
d1ac175e27 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Alec Vercruysse
61e19c2ddf Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE 
To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
d3a988c96c make Cache Flush Logic dependent on !READ_ONLY_CACHE 
read-only caches do not have flush logic since they do not have to
deal with dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
247af17b6b remove ClearValid from cache 
The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
3867142f10 change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe 
the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
4993b1b426 turn off ce coverage for ram1p1rwe 
According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.

For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.

Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
277f507e9a add ram1p1rwe for read-only cache ways (remove byte-enable) 
- increases coverage
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
c0206cfcb3 fix typo in cachway setValid input comment 2023-04-05 11:48:18 -07:00
Alec Vercruysse
270200bc1c put cacheLRU coverage explanation on another line 
the `: explanation` syntax was not working
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
c41f4d2e7b Exclude CacheLRU log2 function from coverage 2023-04-05 11:48:18 -07:00
Ross Thompson
7c2512446c Progress on bug 203. 2023-04-05 13:20:04 -05:00
Kevin Thomas
5e5842893b Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
David Harris
b7b1f2443f Fixed WFI to commit when an interrupt occurs 2023-04-04 09:32:26 -07:00
Ross Thompson
c21a5aaaf7
Merge pull request #194 from davidharrishmc/dev 
Bit manipulation support in ImperasDV.  Test improvements.
 2023-04-04 09:13:27 -05:00
Kevin Kim
d7deed1690
Merge branch 'openhwgroup:main' into zbc_optimize 2023-04-03 23:45:49 -07:00
Kevin Kim
ce8a401a84 reduced mux3 to mux2 for input signal to clmul 2023-04-03 22:53:46 -07:00
David Harris
57ee9f3a5a Merged priv.S edits 2023-04-03 18:07:14 -07:00
Sydeny
8cfd221444 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-03 13:41:55 -07:00