81 Commits

Author	SHA1	Message	Date
bbracker	51e68819c4	fix up PLIC and UART checkpointing	2022-03-07 23:48:47 -08:00
bbracker	c2ac18b5de	change testbench-linux.sv to use new shared location of disassembly files	2022-03-07 20:04:08 -08:00
David Harris	9fd861a9ee	removed more old 64priv tests	2022-03-04 03:57:19 +00:00
bbracker	1c5697874f	comment out nonfunctioning CSR-PERMISSIONS-M test	2022-03-04 00:11:55 +00:00
bbracker	443dd40ea8	remove imperas32p tests	2022-03-04 00:06:18 +00:00
bbracker	e28ca531e0	fix peripheral test and add it to regression	2022-03-02 23:44:39 +00:00
bbracker	d7b8c9d877	add rv32a tests to regression	2022-03-02 17:54:55 +00:00
bbracker	5f5cc514b8	fix buildroot checkpointing and add it back to regression	2022-03-02 16:00:19 +00:00
bbracker	4f22a55dd4	add LRSC test and add wally64a to regression	2022-03-02 07:09:37 +00:00
bbracker	04ace8c154	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
bbracker	d620fb4442	deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test	2022-03-01 00:37:46 +00:00
David Harris	f314e60dc8	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
bbracker	a6047697c3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-22 04:27:50 +00:00
bbracker	6caa97bb26	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00
Kip Macsai-Goren	d1578d8356	added scratch register tests for 64 and 32 bits	2022-02-21 07:03:12 +00:00
Kip Macsai-Goren	4113d64b19	added 32 bit pma tests to regression even though they've been working fo a while	2022-02-18 19:43:24 +00:00
Kip Macsai-Goren	c3523dfa15	Added misa test for both 32 and 64 bits	2022-02-18 19:41:50 +00:00
Kip Macsai-Goren	6c1383e2a0	added CSR permission and minfor to 32 bit tests	2022-02-15 20:19:14 +00:00
Kip Macsai-Goren	5df0a9531f	merged test macros in with 32 bit tests	2022-02-15 20:19:14 +00:00
David Harris	ed8ac3d881	Just needed to recompile - all good. Now removed uretM because N-mode is depricated	2022-02-15 19:48:49 +00:00
Kip Macsai-Goren	9266bc382e	light cleanup for privileged tests	2022-02-15 17:06:16 +00:00
David Harris	9ad3f26365	Restored E tests to makefrag	2022-02-08 16:41:11 +00:00
David Harris	e5097e67d4	Fixed TIM tests; rv32e test still failing	2022-02-08 15:24:37 +00:00
David Harris	e9a519a228	Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail	2022-02-08 12:40:02 +00:00
David Harris	096242a6d8	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
David Harris	72c2166223	Lab 3 file cleanup	2022-02-08 10:26:37 +00:00
Kip Macsai-Goren	38b75e85a0	added new tests to make and testbench	2022-02-06 19:47:22 +00:00
bbracker	27dd363a85	remove sporadic tabs from tests.vh so that it is now only spaces	2022-02-05 23:07:38 +00:00
David Harris	23868a33bc	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
David Harris	16b5fee795	RV32e tests	2022-02-04 14:30:36 +00:00
David Harris	e92461159d	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	9e0055cbb9	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	c12407ba6a	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	2f7cf2bc7f	Fixed testbench so coremark stops.	2022-02-02 11:37:48 -06:00
Ross Thompson	ae36931bb2	Added correct stop condition for coremark.	2022-02-02 09:53:51 -06:00
Ross Thompson	2d8b0aa650	Modified makefiles to generate function address to name mappings for modelsim.	2022-02-01 18:25:03 -06:00
Ross Thompson	058b368a22	Improved function_radix to not printout warnings when no valid function is found.	2022-02-01 18:03:09 -06:00
Ross Thompson	138b17a399	Setup the main regression test to be able to handle coremark.	2022-02-01 17:00:11 -06:00
Ross Thompson	a04aa283cb	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Ross Thompson	c1311ca56a	Fixed modelsim warning with linux simulation.	2022-01-31 12:57:02 -06:00
Ross Thompson	1476a79ea2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-31 12:17:37 -06:00
Ross Thompson	e35a8299ec	Encapsulated dtim.	2022-01-31 11:23:55 -06:00
Kip Macsai-Goren	1077cf08b0	added machine info test that uses new test library	2022-01-31 05:54:43 +00:00
David Harris	2d112698b7	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
David Harris	62e5c7fd13	Comments in LSU code about restructuring	2022-01-27 15:53:59 +00:00
David Harris	c60bb68bff	Testgen working for Lab 2	2022-01-26 18:01:51 +00:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	5842d780a7	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00
David Harris	f7f3882cb8	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00