Katherine Parry
|
26bad083ad
|
all rv64f instructions except convert, divide, square root, and FLD pass
|
2021-06-20 20:24:09 -04:00 |
|
David Harris
|
72d8d34e3c
|
allow all size memory access in CLINT; added underscore to peripheral address symbols
|
2021-06-18 08:05:50 -04:00 |
|
David Harris
|
9dd3857c26
|
Fixed lint WIDTH errors
|
2021-06-09 20:58:20 -04:00 |
|
bbracker
|
17960a6484
|
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
|
2021-06-08 12:41:25 -04:00 |
|
bbracker
|
5026a42fac
|
* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
|
2021-06-08 12:32:46 -04:00 |
|
Kip Macsai-Goren
|
46b2b19792
|
implemented simpler page mixers, cleaned up a bit
|
2021-06-07 18:32:34 -04:00 |
|
Katherine Parry
|
e4db6ea6f5
|
fixed lint warnings for fpu and lzd
|
2021-06-05 12:06:33 -04:00 |
|
Katherine Parry
|
19116ed889
|
Double-precision FMA instructions
|
2021-06-04 14:00:11 -04:00 |
|
Kip Macsai-Goren
|
a84dd6dfc5
|
added tests for SV48 and translation off with vmem
|
2021-06-03 14:28:52 -04:00 |
|
James E. Stine
|
bccdd2c137
|
Updates to muldiv.sv for 32-bit div/rem
|
2021-06-01 15:31:07 -04:00 |
|
Ross Thompson
|
8f9680556f
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-06-01 11:33:12 -05:00 |
|
Ross Thompson
|
5bc2a8b346
|
Now have global history working correctly.
|
2021-06-01 10:57:43 -05:00 |
|
James E. Stine
|
927aec34a2
|
Modify muldiv.sv to handle W instructions for 64-bits
|
2021-05-31 23:27:42 -04:00 |
|
bbracker
|
a45b61ede9
|
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
|
2021-05-28 23:11:37 -04:00 |
|
Katherine Parry
|
0646e08609
|
classify unit created and passes imperas tests
|
2021-05-27 18:53:55 -04:00 |
|
Katherine Parry
|
65eca433b6
|
All compare instructions pass imperas tests
|
2021-05-27 15:23:28 -04:00 |
|
Katherine Parry
|
bd05de0dbb
|
FADD and FSUB imperas tests pass
|
2021-05-26 12:33:33 -04:00 |
|
Kip Macsai-Goren
|
ba134eb166
|
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
|
2021-05-24 20:59:26 -04:00 |
|
James E. Stine
|
1704fdc877
|
Mod for DIV/REM instruction and update to div.sv unit
|
2021-05-24 19:29:13 -05:00 |
|
Ross Thompson
|
3c5e87d6c2
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-24 14:28:41 -05:00 |
|
Katherine Parry
|
03aea055fa
|
FMV.X.D imperas test passes
|
2021-05-24 14:44:30 -04:00 |
|
Ross Thompson
|
daf344f1ba
|
Updated branch predictor tests/benchmarks.
|
2021-05-24 11:13:33 -05:00 |
|
Katherine Parry
|
55f22979ca
|
FSD and FLD imperas tests pass
|
2021-05-23 18:33:14 -04:00 |
|
bbracker
|
142b02b30a
|
improved PLIC test organization
|
2021-05-21 15:13:02 -04:00 |
|
James E. Stine
|
49a4097d97
|
Minor testbench updates to rv64icfd
|
2021-05-21 09:41:21 -05:00 |
|
James E. Stine
|
47487a625f
|
Update to testbench-imperase for rv64icfd
|
2021-05-21 09:28:44 -05:00 |
|
James E. Stine
|
694e21541b
|
Update to FLD/FSD testbench
|
2021-05-21 09:26:55 -05:00 |
|
James E. Stine
|
474d479280
|
Update to rv64icfd wally-config to run through FP tests
|
2021-05-21 09:22:17 -05:00 |
|
Katherine Parry
|
67a41748ba
|
FMV.D.X imperas test passes
|
2021-05-20 22:18:33 -04:00 |
|
Katherine Parry
|
71e4a10efb
|
FMV.D.X imperas test passes
|
2021-05-20 22:17:59 -04:00 |
|
bbracker
|
fd4fae0406
|
commented out MSTATUS test
|
2021-05-19 12:38:01 -04:00 |
|
James E. Stine
|
f407bee5ae
|
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
|
2021-05-18 13:48:44 -05:00 |
|
David Harris
|
7dcc53dcf5
|
fixed rv64mmu makefile
|
2021-05-18 14:25:55 -04:00 |
|
Katherine Parry
|
409438bc95
|
floating point infinite loop removed from imperas tests
|
2021-05-18 10:42:51 -04:00 |
|
James E. Stine
|
41da78e0b6
|
Mod Imperas Testbench for updated Div/Rem
|
2021-05-17 16:56:30 -05:00 |
|
Domenico Ottolia
|
1c884338b0
|
Forgot to add csr permission tests to testbench
|
2021-05-04 20:20:22 -04:00 |
|
ushakya22
|
6274c8cb80
|
Added mip tests to testbench
|
2021-05-04 15:36:06 -04:00 |
|
Domenico Ottolia
|
14becde792
|
Re-add medeleg tests to testbench
|
2021-05-04 14:42:20 -04:00 |
|
ushakya22
|
da352c81e7
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-04 02:22:17 -04:00 |
|
ushakya22
|
66344f0604
|
Added MIE tests to testbench
|
2021-05-04 02:22:01 -04:00 |
|
Domenico Ottolia
|
2c39c0a6a5
|
Minor tweaks to mcause & scause tests
|
2021-05-04 01:33:49 -04:00 |
|
David Harris
|
7c2481bea6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-04 01:19:57 -04:00 |
|
David Harris
|
4db3780ebb
|
Fixed testbench to produce error when signature.output doesn't exist
|
2021-05-04 01:19:44 -04:00 |
|
Thomas Fleming
|
39135f221e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-04 01:14:13 -04:00 |
|
Domenico Ottolia
|
1556cc5b9f
|
Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE
|
2021-05-04 01:04:12 -04:00 |
|
Domenico Ottolia
|
84911e6345
|
Fix 32 bit privileged tests!!!
|
2021-05-04 00:16:19 -04:00 |
|
Thomas Fleming
|
4f5ef65aeb
|
Restore original order of tests
|
2021-05-03 23:50:21 -04:00 |
|
Thomas Fleming
|
d53afc8510
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-03 23:15:39 -04:00 |
|
Thomas Fleming
|
1f6db293fa
|
Enable mmu tests in testbench
|
2021-05-03 23:15:23 -04:00 |
|
Domenico Ottolia
|
12d8ff617b
|
Run all tests
|
2021-05-03 22:38:59 -04:00 |
|