Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 01:44:41 +00:00
Code Issues Packages Projects Releases Wiki Activity
1,982 Commits 4 Branches 2 Tags 53 MiB
5a2a2ca4f5
Commit Graph

424 Commits

Author SHA1 Message Date
bbracker
5a2a2ca4f5 increase buildroot progress expecttions; increase timeout to 20 hours 2021-11-19 12:52:11 -08:00
David Harris
b996598b37 CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
b49c419d0b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:28:33 -08:00
Kevin Kim
d4e9376854 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 12:18:25 -08:00
Kevin Kim
34b3cc1c8d root level makefile added 2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
3f76549a7d renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
David Harris
5a521e28ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
David Harris
f96152fa31 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
Kevin Kim
a7684f1b59 Makefile added in regression directory: 
-cd's into imperas then runs make commands, finally running the tvLinker script
 2021-11-09 10:55:48 -08:00
bbracker
1597e0dac6 increase expectations for buildroot and timeout count 2021-11-06 14:57:29 -07:00
bbracker
e4cf044932 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
David Harris
910957704b Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
c306884e2c Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
bbracker
38d26e857b fix buildroot graphical sim 2021-10-31 18:33:43 -07:00
David Harris
717f9d48e9 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
0421b7af56 Changes for floating point sims 2021-10-27 10:37:35 -07:00
David Harris
f793dd7a5e removed unused signal from wave.do 2021-10-26 09:02:22 -07:00
bbracker
f39a509b5b adapt testbench linux to use reset_ext 2021-10-25 13:26:44 -07:00
bbracker
2c9c9328a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
c61cbf9618 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
David Harris
47124f36c8 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
9423b90780 switch linux graphical sim over to Ross's waves 2021-10-24 18:39:23 -07:00
bbracker
4544d28bc9 or actually needed to reduce expectations of buildroot 2021-10-24 06:59:34 -07:00
bbracker
23bff55c6e increase regression's expectations of buildroot 2021-10-24 06:50:22 -07:00
bbracker
366cb12a13 buildroot do scripts now compile flops 2021-10-23 23:14:59 -07:00
bbracker
3b63dde570 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
d6fb441666 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
67f3fc9962 wrapping up lint cleanup; many unused signals removed 2021-10-23 12:15:14 -07:00
David Harris
bf3eb7b814 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
James E. Stine
eb64a7f0c9 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
bbracker
886a650da4 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
David Harris
a8ce4568aa Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
a077735ecc Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
bbracker
50e5b0a8f4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 13:12:44 -07:00
bbracker
efe9f5d857 make regression expect what buildroot is actually able to reach 2021-10-10 13:12:36 -07:00
David Harris
bfe8bf3855 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
bbracker
64a3043a88 update wave-do 2021-10-07 19:16:52 -04:00
James E. Stine
739e17ddac Add generic wave command file 2021-10-06 13:17:49 -05:00
James E. Stine
658dcc8c1b Update to testbench for FP stuff 2021-10-06 13:16:38 -05:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
Ross Thompson
d09b381183 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872 Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00