3337 Commits

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Author	SHA1	Message	Date
David Harris	581d841653	Cause simplification	2022-05-12 23:29:35 +00:00
David Harris	2a3f545e0c	Cause simplification	2022-05-12 23:27:02 +00:00
David Harris	c2b9fc0d8e	trap/csr cleanup	2022-05-12 22:26:21 +00:00
David Harris	292d1f33da	More trap/csr simplification	2022-05-12 22:06:03 +00:00
David Harris	662fffa830	More trap/csr simplification	2022-05-12 22:04:20 +00:00
David Harris	16b86c199c	More trap/csr simplification	2022-05-12 22:00:23 +00:00
David Harris	5f358a37c6	More trap/csr simplification	2022-05-12 21:55:50 +00:00
David Harris	21ac969c7d	Simplifying trap/csr interface	2022-05-12 21:50:15 +00:00
David Harris	072c464dc1	Simplified MTVAL logic	2022-05-12 21:36:13 +00:00
David Harris	14f9f41d2d	Partitioned privileged pipeline registers into module	2022-05-12 20:45:45 +00:00
David Harris	78448c7053	privileged cleanup	2022-05-12 20:21:33 +00:00
mmasserfrye	31f372e7b3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-12 20:20:40 +00:00
mmasserfrye	a10b8e47af	cleaned lint for ppa.sv	2022-05-12 20:20:05 +00:00
David Harris	dd61afb7dc	Formatting cleanup	2022-05-12 18:37:47 +00:00
mmasserfrye	01685b982c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-12 18:08:20 +00:00
mmasserfrye	b089ee26ee	renamed madzscript, modified ppa.sv alu and shifter	2022-05-12 18:05:02 +00:00
David Harris	fde8375fbd	Moved Breakpoint and Ecall fault logic into privdec	2022-05-12 16:45:53 +00:00
David Harris	2ceed15bd5	Moved TLB Flush logic into privdec	2022-05-12 16:41:52 +00:00
David Harris	1e5d94bbab	Moved WFI timeout into privdec	2022-05-12 16:22:39 +00:00
David Harris	39ceb3a550	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	e81e530f68	More signal cleanup	2022-05-12 15:39:44 +00:00
David Harris	ce24c080d5	More unused signal cleanup	2022-05-12 15:26:08 +00:00
David Harris	5670f77de2	More unused signal cleanup	2022-05-12 15:21:09 +00:00
David Harris	4edf9b6355	More unused signal cleanup	2022-05-12 15:15:30 +00:00
David Harris	1aa3e65bae	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	e2e63ca9a8	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	f17501ed8c	Removing unused signals	2022-05-12 14:36:15 +00:00
David Harris	545d46acb9	Simplifed mstatus.TSR handling	2022-05-12 14:09:52 +00:00
David Harris	d353cef432	Removed unused ch5 assembly example	2022-05-12 14:05:27 +00:00
David Harris	1e7401daa0	Fixed typo in csrm	2022-05-12 06:55:39 -07:00
mmasserfrye	999754801c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-12 07:24:04 +00:00
mmasserfrye	6cba6a92ba	filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv	2022-05-12 07:22:06 +00:00
David Harris	aa452b2f38	Moved some privileged tests to be simulated.	2022-05-12 04:45:41 +00:00
David Harris	9999f69922	Added MCONFIGPTR CSR hardwired to 0	2022-05-12 04:31:45 +00:00
David Harris	b2c921ee7b	Added examples/asm/trap trap handler example	2022-05-12 04:31:00 +00:00
David Harris	9dd378098f	merged ppa.sv	2022-05-11 18:14:16 +00:00
David Harris	1f761c4e06	PPA script progress	2022-05-11 18:11:51 +00:00
mmasserfrye	552a55d631	ed ... modified ppa.sv	2022-05-11 16:22:12 +00:00
mmasserfrye	6fad0dc8ed	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-05-11 16:16:23 +00:00
mmasserfrye	68da2f5fa1	modified ppa.sv to match module name and added madzscript	2022-05-11 16:13:01 +00:00
David Harris	8166fd772e	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	137b411bea	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	490902a655	Updated PPA experiment	2022-05-10 23:09:42 +00:00
David Harris	bb24aebebd	Initial PPA study	2022-05-10 20:48:47 +00:00
David Harris	04fd22aeb0	endian swapper	2022-05-08 06:51:50 +00:00
David Harris	4f1b0fdc64	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	1a5bfcf078	Fixed bug in delegated interrupts not being taken	2022-05-08 04:50:27 +00:00
David Harris	a516f89f22	WFI terminates when an interrupt is pending even if interrupts are globally disabled	2022-05-08 04:30:46 +00:00
David Harris	412d4656ed	Zero'd wfiM when ZICSR not supported to fix hang in E tests	2022-05-05 15:32:13 +00:00
David Harris	7f42ff06d2	SFENCE.VMA should be illegal in user mode	2022-05-05 15:15:02 +00:00