Ross Thompson
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da499aafc0
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Merge branch 'main' of github.com:ross144/cvw
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2023-07-07 13:25:00 -05:00 |
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Kevin Kim
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23bb96f857
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divremsqrt now includes f64
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2023-07-06 21:23:46 -07:00 |
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Kevin Kim
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f170f93576
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Merge branch 'divsqrtrem' of https://github.com/kipmacsaigoren/cvw into divsqrtrem
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2023-07-06 19:49:14 -07:00 |
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Kevin Kim
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6851233303
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extraneous files
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2023-07-06 19:49:13 -07:00 |
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Kevin Kim
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8d898b16c7
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fixed sticky bit logic bug
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2023-07-06 19:48:25 -07:00 |
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Ross Thompson
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40b2f7ff9c
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Updated comments.
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2023-07-06 15:24:26 -05:00 |
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Ross Thompson
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dc50ddd75e
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Removed unused parameter.
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2023-07-06 14:57:07 -05:00 |
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Ross Thompson
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0394f3232f
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-07-06 14:55:43 -05:00 |
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David Harris
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74a573cedd
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Removed outdated commment about endianness
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2023-07-06 12:41:46 -07:00 |
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David Harris
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29e62f05a4
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Removed MTINST, which is not used in a system without a hypervisor
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2023-07-06 12:40:53 -07:00 |
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Ross Thompson
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18278b7f4d
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It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga.
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2023-07-06 14:07:37 -05:00 |
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Ross Thompson
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ba9d5287d9
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This is at least functionally correct, but has verilator lint issues.
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2023-07-06 11:53:34 -05:00 |
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Ross Thompson
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930aed0898
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closer, but the wally32/64priv tests are failing.
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2023-07-05 17:47:38 -05:00 |
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Ross Thompson
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c0fdd3fbca
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Partially solved fpga boot.
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2023-07-05 17:30:55 -05:00 |
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Ross Thompson
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60cc5c97f4
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Merge pull request #355 from davidharrishmc/dev
Decoder improvements
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2023-07-05 00:08:49 -04:00 |
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David Harris
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19efc4eda8
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Fixed comment typo
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2023-07-04 11:34:58 -07:00 |
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David Harris
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34ce25ca81
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Commented SVADU requirements for wally32priv mmu tests
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2023-07-04 11:34:07 -07:00 |
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David Harris
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4f07d89d74
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fixed spacing in fdivsqrt
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2023-07-04 11:27:36 -07:00 |
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David Harris
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4c921fc797
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Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder
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2023-07-02 13:29:27 -07:00 |
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David Harris
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e6ba362794
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Added prefetch instructions; sent cbo instructions to LSU
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2023-07-02 10:55:35 -07:00 |
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David Harris
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cc87317189
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Added prefetch signals
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2023-07-02 10:06:58 -07:00 |
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David Harris
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a5c6ae1f78
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Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions
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2023-07-02 09:35:05 -07:00 |
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David Harris
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6a88ac28e4
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Fixed csr typos
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2023-07-02 02:01:40 -07:00 |
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David Harris
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96477a4879
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Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode
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2023-07-02 02:00:27 -07:00 |
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David Harris
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e2708534cd
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Added environment configuration control (menvcfg/senvcfg) of cbo instructions
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2023-07-02 01:52:25 -07:00 |
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David Harris
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4d1ddd0c91
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Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
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2023-07-02 00:34:30 -07:00 |
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David Harris
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110dd42cfb
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improved decoder checking atomic and RW and MW and privileged instructions
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2023-07-02 00:02:03 -07:00 |
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David Harris
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07cf1dd9da
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improved decoder checking atomic instructions
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2023-07-01 23:10:57 -07:00 |
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David Harris
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e05288afd9
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Improved instruction decoding for illegal floating-point loads/stores and fences
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2023-07-01 22:48:04 -07:00 |
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Kevin Kim
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0de69d73c0
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Merge branch 'openhwgroup:main' into divsqrtrem
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2023-06-29 16:28:31 -07:00 |
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Kevin Kim
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654f6dee3f
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debug
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2023-06-29 16:28:01 -07:00 |
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Ross Thompson
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e40bbc8680
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Merge pull request #352 from stineje/main
Change to testbench-fp.sv
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2023-06-29 11:30:01 -04:00 |
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James E. Stine
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76a2a51d68
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Add reset to wave window
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2023-06-29 08:47:16 -05:00 |
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James E. Stine
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407bf44548
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Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion.
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2023-06-29 08:46:11 -05:00 |
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Kevin Kim
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8094c12c80
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fixed port mismatch and conditional postprocessing
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2023-06-28 08:37:12 -07:00 |
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Kevin Kim
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24576f5b0c
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more lints
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2023-06-28 08:32:13 -07:00 |
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Kevin Kim
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1b33913e38
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lint fixes
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2023-06-28 08:28:20 -07:00 |
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Kevin Kim
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f87e1232a4
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added custom test support
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2023-06-27 20:05:30 -07:00 |
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Ross Thompson
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cad1de1241
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-27 11:04:27 -05:00 |
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Ross Thompson
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ebb44e9df3
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Updates for fpga.
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2023-06-27 11:04:20 -05:00 |
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Kevin Kim
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07bfceed36
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- accounted for cvw path change
- funky verilog imports
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2023-06-26 17:45:57 -07:00 |
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Kevin Kim
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7261f54334
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Merge branch 'main' into divsqrtrem
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2023-06-26 17:21:48 -07:00 |
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Ross Thompson
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15ad969498
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Merge pull request #350 from stineje/main
Minor tweak to fix vectors not working for fadd.
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2023-06-26 16:41:01 -04:00 |
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James E. Stine
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012316aa94
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Minor tweak to fix vectors not working for fadd.
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2023-06-26 14:25:44 -05:00 |
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Ross Thompson
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f4a736e4bd
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Merge pull request #349 from stineje/main
Modification to testbench-fp.sv
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2023-06-26 12:51:57 -04:00 |
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James E. Stine
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a0c9ef03ff
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Add signals for ResMatch & CheckNow to sim window that are related to TestFloat operation
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2023-06-26 10:15:46 -05:00 |
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James E. Stine
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83a79b3a40
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Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly
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2023-06-26 10:14:49 -05:00 |
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David Harris
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e230118274
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Merge pull request #348 from stineje/main
Modify testfloat-fp.sv for parameterization
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2023-06-22 13:33:29 -07:00 |
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James E. Stine
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e913c1ea46
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Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works
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2023-06-22 15:27:17 -05:00 |
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James E. Stine
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8f7ba2b8d2
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For some reason this was modified - I probably made a mistake - put back vsim
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2023-06-22 15:26:22 -05:00 |
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