David Harris
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865d5ce0b1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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David Harris
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ecce1e62ee
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changed ideal memory to MEM_DTIM and MEM_ITIM
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2021-12-14 13:05:32 -08:00 |
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Ross Thompson
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500e6ff430
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Fixed buildroot to work with the fpga's merge.
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2021-12-02 18:09:43 -06:00 |
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Ross Thompson
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b03ca464f1
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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Ross Thompson
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a871118116
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Merge branch 'main' into fpga
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2021-11-29 10:10:37 -06:00 |
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Ross Thompson
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5642918ead
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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Ross Thompson
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3fc370654d
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Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
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2021-11-23 10:00:32 -06:00 |
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bbracker
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526aff54a8
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linux testgen refactor
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2021-11-01 14:09:49 -07:00 |
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Ross Thompson
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de4ea16d32
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Merge branch 'main' into fpga
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2021-10-20 16:24:55 -05:00 |
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Shreya Sanghai
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4424006624
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added DESIGN_COMPLIER to forgotten config files
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2021-10-12 10:14:04 -07:00 |
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Ross Thompson
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f6c6cb9ed2
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Merge branch 'main' into fpga
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2021-10-11 18:17:58 -05:00 |
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Ross Thompson
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bfe633d087
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Partially working sd card reader.
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2021-10-11 10:23:45 -05:00 |
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David Harris
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2ae51d1852
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Parameterized number of bits per cycle for integer division
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2021-10-03 01:10:15 -04:00 |
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Ross Thompson
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7ca801113e
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Added debugging directives to system verilog.
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2021-09-27 13:57:46 -05:00 |
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Ross Thompson
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80e37d2291
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Added SDC defines to each config mode.
Added sd_top which is the sd card reader.
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2021-09-24 12:24:30 -05:00 |
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David Harris
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9ae25b0cea
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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86fbe2a654
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Changed configs to support 4 ways set associative caches.
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2021-09-08 12:52:49 -05:00 |
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Ross Thompson
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c749d08542
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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bbracker
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d3059dd04c
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fix UART RX FIFO bug where tail pointer can overtake head pointer
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2021-07-22 02:09:41 -04:00 |
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David Harris
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e1a1a8395e
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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David Harris
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4d40b5faef
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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David Harris
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6bac566bb7
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Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
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2021-07-05 20:35:31 -04:00 |
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David Harris
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80666f0a71
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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ccd9c05303
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Switched to array notation for pmpchecker
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2021-07-04 10:51:56 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ross Thompson
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dbd33465e1
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Merge branch 'main' into bigbadbranch
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2021-07-02 11:52:26 -05:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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bbracker
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83a0a37f8e
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make xCOUNTEREN what buildroot expects it to be
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2021-06-20 09:22:31 -04:00 |
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bbracker
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a3eafc6e5b
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change buildroot config to use relative path for testvectors
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2021-06-18 22:28:07 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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679e507cc6
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Added SUPPORTED to each peripheral in each config file
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2021-06-17 21:36:32 -04:00 |
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bbracker
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d4aeb1c387
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merge
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2021-06-10 10:03:01 -04:00 |
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bbracker
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0321d74562
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attempt to fix regression by adding PMP_ENTRIES to configs
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2021-06-10 09:59:26 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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Kip Macsai-Goren
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a95a7a7b82
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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David Harris
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a26bf37be8
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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David Harris
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0674f5506e
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moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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Kip Macsai-Goren
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40cfa86935
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Edited and added constants to support SV48
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2021-06-01 17:49:45 -04:00 |
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Ross Thompson
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72363f5c66
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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Noah Boorstin
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6954e6df4c
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buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
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2021-04-17 14:44:32 -04:00 |
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Noah Boorstin
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4f97e9e761
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start to add buildroot testbench
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
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2021-04-16 23:27:29 -04:00 |
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