Ross Thompson
52d95d415f
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
Ross Thompson
9b3637bd87
RAS needs to be reset or preloaded. For now I just reset it.
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Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87
Added FlushF to hazard unit.
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Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
f25de68b7d
minor change to wave file.
2021-02-19 09:08:13 -06:00
Ross Thompson
c6ebe7733b
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
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About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Ross Thompson
de9e383bc6
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables.
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Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-17 22:20:28 -06:00
Ross Thompson
5df7e959f3
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
Ross Thompson
78db3654c6
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
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This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
Ross Thompson
3ec1f668fc
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Ross Thompson
30df1cdd25
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
Teo Ene
e878a8bed2
After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to.
2021-02-14 08:58:33 -06:00
Shreya Sanghai
30bfd7534c
added branch tests
2021-02-12 22:40:08 -05:00
Teo Ene
f25b372c32
Quick commit for Ryan / branch / debugging.
2021-02-12 16:06:02 -06:00
Noah Boorstin
423d3a53e5
add reference output for some tests
2021-02-12 18:33:24 +00:00
bbracker
9231646fb3
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Tejus Rao
5158ca4220
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
dfb7333821
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-02-10 20:49:12 -06:00
Teo Ene
8a6de4fb86
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
Teodor-Dumitru Ene
86fcaf0bb1
Added hex code for the pre-compiled, provided, CoreMark binary
2021-02-10 21:22:38 -05:00
Teo Ene
7ca03b2b38
Added freshly compiled CoreMark binaries (elf) and hex code (memfile) for the following extensions:
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- RV64I
2021-02-10 20:12:07 -06:00
ethan-falicov
9edc4b6bfe
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
7e8a58de1a
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
f778f464b7
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
06541260e0
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
James E. Stine
561ffcf56d
Add ppt and mp4 of wavedrom usage
2021-02-09 13:15:29 -06:00
Jarred Allen
403a0d033c
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
81a1eb9a74
merge conflict?
2021-02-07 02:34:49 -05:00
Jarred Allen
48ade25577
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
Jarred Allen
edd758453e
Add test vector set for load instructions
2021-02-06 13:05:59 -05:00
James E. Stine
5c017bac1f
Updates to wavedrom
2021-02-05 10:56:29 -06:00
bbracker
691d651fde
JAL testing
2021-02-05 08:08:42 -05:00
James E. Stine
eb468cc40f
sorry ; last update
2021-02-04 15:20:15 -06:00
James E. Stine
0eae86b6e3
Update as overwrite a file :(
2021-02-04 15:11:06 -06:00
James E. Stine
c259cd2e7e
Updates to wavedrom for typos
2021-02-04 14:49:17 -06:00
James E. Stine
a3bd34eb4b
Add some example wavedrom files - more on the way including ppt
2021-02-04 14:41:42 -06:00
Thomas Fleming
8588a1ed6b
Complete STORE tests
2021-02-04 15:38:22 -05:00
Brett Mathis
79cb7ed571
Parallel FSR's and F CTRL logic
2021-02-04 02:25:55 -06:00
Jarred Allen
ea791cb057
Change busybear test to use work-busybear library
2021-02-03 11:12:47 -05:00
Jarred Allen
743695400d
Start on a test set for loads
2021-02-03 00:37:43 -05:00
David Harris
91f6858de7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
a44c2abb12
Minor tweaks
2021-02-02 19:44:37 -05:00
Jarred Allen
10f023b44d
Refactor regression test
2021-02-02 17:22:29 -05:00
Noah Boorstin
b370be4a8a
Add busybear testbench to nightly regression checking
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If you don't like how I did this please feel free to undo it
2021-02-02 22:05:35 +00:00
Noah Boorstin
00d9e13d68
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
56ff32f857
change undefined syntax in extend.sv
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don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
d56d7a75a6
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
aee44bb343
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
David Harris
4fbb5f0f1b
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
