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1438 Commits

Author SHA1 Message Date
Ross Thompson
52a1d3dafe Name clarifications. 2022-10-05 15:36:56 -05:00
Ross Thompson
aa09b1ef16 Fixed bug with combined dtim+bus. 2022-10-05 15:16:01 -05:00
Ross Thompson
98521d073f Possibly have working dtim + bus config. 2022-10-05 15:08:20 -05:00
Ross Thompson
b01ee070bd Updated wavefile. 2022-10-05 14:55:40 -05:00
Ross Thompson
bf6f0e7219 Fixed bug in EBU. 2022-10-05 14:51:12 -05:00
Ross Thompson
cabcb5e89e Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS. 
Don't use this commit as the rv32i tests are not passing.
 2022-10-05 14:51:02 -05:00
Ross Thompson
5e09d1cca7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-05 14:03:44 -05:00
David Harris
29033dc334 Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests. 2022-10-05 11:46:52 -07:00
Ross Thompson
ea70e1c598 Optimized the ebu's beat counting. 2022-10-05 10:58:23 -05:00
Ross Thompson
294645a49f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-04 17:38:49 -05:00
Ross Thompson
494f8b94f4 Reordered the eviction and fetch in cache so it follows a more logical order. 2022-10-04 17:36:07 -05:00
Ross Thompson
18e739befc Modified cache lru to not have the delayed write. 2022-10-04 15:14:58 -05:00
Kip Macsai-Goren
c18c181fc0 fixed endianness mstatush problem, passes make, not regression 2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
3f6d05f7a2 addded renamed file 2022-10-04 17:37:05 +00:00
Kip Macsai-Goren
9a0b98037b Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
fb464b9546 Renamed endianswap to match module name 2022-10-04 17:33:49 +00:00
Ross Thompson
0ed0c18aa1 Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered. 2022-10-02 16:21:21 -05:00
Ross Thompson
d08c29e3c5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-10-01 15:01:22 -05:00
Ross Thompson
41ab4850e1 Disable IFU bus access on TrapM. 2022-10-01 14:54:16 -05:00
Ross Thompson
e27fcb1577 Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage. 2022-09-29 18:37:34 -05:00
David Harris
657f16dfd1 Adding start signals for integer divider to fdivsqrt 2022-09-29 16:30:25 -07:00
Ross Thompson
2c0132aa9c Renamed signals in EBU. 2022-09-29 18:29:38 -05:00
cturek
e8a869e0e7 Added integer inputs and flags to divsqrt 2022-09-29 23:08:27 +00:00
Ross Thompson
58d597b614 Simplification to EBU. 2022-09-29 18:06:34 -05:00
Ross Thompson
d81af3bca8 Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore. 2022-09-29 11:54:03 -05:00
Ross Thompson
32449dfe97 Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
Ross Thompson
4db017dac3 Possible fix for ifu/lsu arbiration issue. 2022-09-27 17:24:35 -05:00
Ross Thompson
4062fe56c0 Possible fix to the bus cache interaction. 2022-09-27 11:34:33 -05:00
Ross Thompson
07bb11518e Found a hidden bug in the cache to bus fsm interlock. 2022-09-26 17:41:30 -05:00
Ross Thompson
996c4ca8f2 renamed ahbmulticontroller to ebu. 2022-09-26 14:37:18 -05:00
Ross Thompson
8ed173a5f5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-26 12:49:16 -05:00
Ross Thompson
0fcc314d06 Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed. 2022-09-26 12:48:26 -05:00
David Harris
713df785d1 changed always_ff to always in sram1p1rw to fix testbench complaint 2022-09-25 19:56:40 -07:00
Ross Thompson
38edbde966 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
2eaf3af6c7 Removed the write first sram model. 2022-09-22 16:12:08 -05:00
Ross Thompson
cec50ce208 The valid and dirty bits match the SRAM implementation now. 2022-09-22 16:09:09 -05:00
Ross Thompson
b48d6b5e1f Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
89e6ddfa4e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 18:24:06 -05:00
Ross Thompson
99e01dd31f Cleaned up the IFU and LSU around dtim and irom address calculation. 2022-09-21 18:23:56 -05:00
David Harris
d6297a2f2e For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc 2022-09-21 13:30:35 -07:00
David Harris
e49e99548a Fixed testbench-fp to support all again 2022-09-21 13:19:48 -07:00
David Harris
46680b80a7 Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
Ross Thompson
f57b0b9950 Updated IROMAdr logic. 2022-09-21 12:42:43 -05:00
Ross Thompson
0add170b44 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 12:36:52 -05:00
Ross Thompson
3fb0a13fe2 Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
David Harris
030fb79a3c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 10:35:11 -07:00
David Harris
cb4c3ff1ce Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest 2022-09-21 10:35:08 -07:00
Ross Thompson
66c45949b5 Renamed brom1p1r to rom1p1r. 
removed used file bram2p1r1w.sv.
 2022-09-21 12:31:20 -05:00
Ross Thompson
832658838d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 12:20:12 -05:00
Ross Thompson
ac864a6ca3 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00