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Author SHA1 Message Date
Ross Thompson
4fed1d5e3d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-04 11:28:26 -06:00
Ross Thompson
d7a65b2576 Updates to imperas test bench. 2023-02-04 11:28:23 -06:00
David Harris
835f793db9 Merge pull request #62 from davidharrishmc/dev 
../synthDC/Makefile
 2023-02-04 04:29:56 -08:00
David Harris
be08523ba0 Added license headers 2023-02-04 04:29:27 -08:00
David Harris
f89e642312 ../synthDC/Makefile 2023-02-04 04:19:09 -08:00
David Harris
52e028fc7a Merge pull request #53 from davidharrishmc/dev 
Removed pipelined hierarchy and renamed regression to sim
 2023-02-04 04:15:02 -08:00
David Harris
6b9ae4fc89 Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
David Harris
e831baf335 Improved illegal NaN-box detection and formatted fsgninj 2023-02-04 03:42:20 -08:00
David Harris
18750e0f0a Merge pull request #61 from mmasserfrye/main 
USE_SRAM parameter, makefile config cleaning
 2023-02-04 03:28:44 -08:00
Madeleine Masser-Frye
4be41ae25c finishing the job of the last commit 2023-02-04 10:24:01 +00:00
Madeleine Masser-Frye
b78ce62748 added use sram parameter, cleaned up config writing, added single synth functionality to wallySynth 2023-02-04 09:50:36 +00:00
David Harris
fa276d67b4 Merge pull request #60 from ross144/main 
Optimized PCLink logic.
 2023-02-03 16:42:27 -08:00
Ross Thompson
f5468ebd7a Replaced PCLinkX registers with a +2/4 adder in the execution stage. 
David and I estimate this is lower hardware cost.
 2023-02-03 18:19:47 -06:00
Ross Thompson
583d87afc7 Change CurrPtr to Ptr in RAS. 2023-02-03 17:40:20 -06:00
David Harris
34fbfeb5cd Removed redundant line from synthesis makefile 2023-02-03 08:36:51 -08:00
David Harris
97ee3732fe Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-03 08:36:11 -08:00
David Harris
4dca69f205 Updated division radix test script with paths, but script is out of date for files it manipulates 2023-02-03 08:36:03 -08:00
David Harris
1763de52ea Merge pull request #54 from ross144/main 
Fixed issue #50, itlb and dcache flush interlock
 2023-02-03 06:30:30 -08:00
Ross Thompson
4547da80ea Fixed bug #49. 
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
 2023-02-03 00:39:26 -06:00
Ross Thompson
659b511616 Lee Moore found another bug using imperas. 
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
 2023-02-02 23:52:21 -06:00
David Harris
644dfe7463 Removed lab1matrix solutions 2023-02-02 19:40:41 -08:00
David Harris
e6bfcd14fa Merged with memories 2023-02-02 14:50:46 -08:00
David Harris
80f42a8638 Renamed regression to sim 2023-02-02 14:48:23 -08:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
David Harris
3531afa5cf Update README.md 2023-02-02 12:59:28 -08:00
James E. Stine
4b2a13bc44 Merge pull request #52 from stineje/main 
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
 2023-02-02 13:55:17 -06:00
James Stine
924e55325c Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22 2023-02-02 13:54:25 -06:00
David Harris
e4f2e96449 Merge pull request #51 from stineje/main 
Modify generic/mem for rv32gc ram2
 2023-02-02 11:41:32 -08:00
James Stine
9a5023a17e Modify generic/mem for rv32gc ram2 2023-02-02 13:28:18 -06:00
David Harris
30ba42d498 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-02 10:28:40 -08:00
David Harris
0af2ff969c Merge pull request #48 from ross144/main 
Fixed bug #47, ecall and ebreak don't commit
 2023-02-02 06:58:07 -08:00
Ross Thompson
3c8f07ffa1 Merge branch 'main' of github.com:ross144/cvw 2023-02-02 08:52:48 -06:00
Ross Thompson
3838ab232b Fixed bug #47 discovered by Lee Moore. 
ECALL and EBREAK do not commit their results.
 2023-02-02 08:52:06 -06:00
Ross Thompson
7f207527ce Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-02 08:48:19 -06:00
Ross Thompson
279c62c402 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-01 19:24:10 -06:00
David Harris
0a540495f6 Removed O2 from fir Makefile to be consistent with lab. 2023-02-01 15:43:52 -08:00
David Harris
c5578cc2fb Merge pull request #45 from stineje/main 
Update ram2 and other memories and associated wrappers
 2023-02-01 15:06:30 -08:00
James Stine
fc5692629a Update ram2 and other memories and associated wrappers 2023-02-01 17:03:48 -06:00
Ross Thompson
3276353b8c Minor branch predictor bug fix. 2023-02-01 10:59:38 -06:00
Ross Thompson
51a2a71410 Removed unused signal. 2023-02-01 10:27:58 -06:00
David Harris
8601f04397 Fixed typo in DC setup for memories 2023-02-01 05:49:30 -08:00
David Harris
e820d1938a Only add memory libraries when targeting 28nm 2023-02-01 05:06:56 -08:00
David Harris
733b877f1d Merge pull request #36 from davidharrishmc/dev 
RV32imc configuration
 2023-02-01 04:44:36 -08:00
David Harris
ce82d8d550 Fixed merge conflict to get synthesis working again 2023-02-01 04:43:57 -08:00
David Harris
39942bbc45 Merge pull request #43 from mmasserfrye/main 
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
 2023-02-01 04:13:37 -08:00
Ross Thompson
6fb624950e Minor change to btb. 2023-02-01 00:24:54 -06:00
Madeleine Masser-Frye
57b35c293d added memories (not tested) 2023-02-01 06:08:27 +00:00
Ross Thompson
241d63ce1f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-01 00:01:14 -06:00
Madeleine Masser-Frye
a81d569e1a increased bpred size to (2^) 5 2023-02-01 05:51:31 +00:00
Madeleine Masser-Frye
d734f7af92 updated synth makefile to change all relevant 
ram ranges to 1FF
 2023-02-01 05:40:35 +00:00