Ross Thompson
4eff75449a
Maybe have the baseline local history predictor working.
2023-05-01 15:45:27 -05:00
Ross Thompson
7437cb67e5
Merge branch 'main' into localhistory
2023-05-01 10:35:50 -05:00
Ross Thompson
67539a4af1
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-30 23:30:13 -05:00
David Harris
6253c042b2
Merged coverage exclusions for PMP
2023-04-28 08:04:25 -07:00
David Harris
194b848fbf
PMA Checker coverage
2023-04-28 07:53:59 -07:00
David Harris
af7959a3e2
Commenting
2023-04-28 07:52:08 -07:00
David Harris
9843223ddd
Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues
2023-04-28 07:03:46 -07:00
Ross Thompson
d44251098f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-27 16:38:36 -05:00
David Harris
ca61cff33f
CSR code cleanup
2023-04-27 14:12:57 -07:00
David Harris
a929656d9a
Renamed byteUnit to byteop
2023-04-27 14:10:46 -07:00
Ross Thompson
7c0eb16e62
Fixed bug in cacheLRU when NUMWAYS = 2.
2023-04-27 14:30:01 -05:00
Liam
4d8eafd27d
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
David Harris
6a5895e09f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-27 07:30:07 -07:00
Alexa Wright
09095422d0
Merge branch 'openhwgroup:main' into main
2023-04-26 16:26:30 -07:00
Alexa Wright
6ee8a9c0bd
Added better comment for the exclusion in privdec.sv
2023-04-26 16:25:55 -07:00
David Harris
0eb8dd7935
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-26 15:40:11 -07:00
David Harris
ea3e3a1469
Merge pull request #283 from SydRiley/main
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Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
2023-04-26 15:40:01 -07:00
Sydeny
5bcd57dab9
Addressing Redundant logic around BadNanBox, fpu coverage from 96.61% to 96.77%
2023-04-26 14:35:43 -07:00
David Harris
7cc26861cd
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-26 05:53:42 -07:00
Alec Vercruysse
5612f30029
Cacheway Exclude FlushStage=1 when SetValidWay=1
...
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).
My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
2023-04-25 20:30:46 -07:00
Alexa Wright
59d913949f
Excluded and added coverage for WFI test case.
2023-04-25 17:06:57 -07:00
Alec Vercruysse
857956ac1e
Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign
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FlushWay is always 1 for one way, but by default it is only 1 for
way 0.
The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
2023-04-25 17:02:53 -07:00
David Harris
a5087818ba
Commented about Sstvecd trap vector alignment
2023-04-24 12:20:33 -07:00
David Harris
ee6a3f49f0
Added M suffix in atomic
2023-04-24 12:19:56 -07:00
Ross Thompson
5777b90407
Might actually have a correct implementation of local history branch prediction.
2023-04-24 13:05:28 -05:00
Ross Thompson
e81445be5d
Fixed the local branch predictor so that it at least compiles.
2023-04-24 11:06:53 -05:00
Diego Herrera Vicioso
d29dc30288
Excluded coverage for impossible cases in wficountreg and status.MPRV
2023-04-24 02:06:53 -07:00
David Harris
52f49ed24d
Fault on writes to odd-numbered PMPCFG in RV64
2023-04-22 15:32:39 -07:00
David Harris
3b299fb77a
Removed unproven fdivsqrt exclusion
2023-04-22 15:27:05 -07:00
David Harris
086556310c
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
David Harris
063e41806e
Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right
2023-04-22 10:07:48 -07:00
David Harris
8a59a4ce94
fdivsqrt cleanup
2023-04-20 17:35:01 -07:00
David Harris
86107e6136
continued cleanup
2023-04-20 16:48:23 -07:00
David Harris
33c0f64457
Reordered fdivsqrtpreproc to follow logic
2023-04-20 16:38:47 -07:00
David Harris
2c47268f50
Started fdivsqrtpreproc flow organization
2023-04-20 16:25:19 -07:00
David Harris
f2ae770e17
Fmv h/q comments in controller
2023-04-20 16:24:58 -07:00
David Harris
b9d641f13a
Merge pull request #256 from cturek/main
...
Simplifying fds to follow diagram
2023-04-20 16:07:22 -07:00
David Harris
3a8d2db194
Merge pull request #262 from SydRiley/main
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removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 14:49:50 -07:00
Sydeny
a132ffa7f7
removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 13:30:12 -07:00
Alec Vercruysse
faaf266558
CacheFSM logic simplification for AMO operations
...
Ran this by Ross.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
de93bd6937
D$ scope-specific coverage exclusions (I$ logic that never fires)
...
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.
Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.
There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Cedar Turek
49356aa4ca
created fdivsqrtcycles, moved cycles calculation from FSM to preproc
2023-04-18 16:14:45 -07:00
Cedar Turek
b1dd1a627f
gave integer bits to D instead of adding manually everywhere
2023-04-18 15:41:04 -07:00
Cedar Turek
914baf6bb1
moved D flop to preproc
2023-04-18 15:14:17 -07:00
Sydeny
ee5deb10a7
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-17 13:51:16 -07:00
David Harris
a413b5c6ca
Merge pull request #251 from masonadams25/main
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Removed redundent expression to increase coverage
2023-04-17 12:37:27 -07:00
Mason Adams
56575cb45e
Removed redundent expression to increase coverage
2023-04-17 14:13:26 -05:00
David Harris
64fe318cb0
merged coverage exclusions
2023-04-17 10:17:48 -07:00
Diego Herrera Vicioso
16fd17be39
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Sydeny
0dc50536ef
trimming comments on fctrl bug fixes
2023-04-15 00:48:32 -07:00
