184 Commits

Author	SHA1	Message	Date
Kip Macsai-Goren	6fdd603ba1	added potential fix to overrun error and fifo interrupt error. test passes	2022-11-06 22:01:02 -08:00
Kip Macsai-Goren	b42fc7ec6d	fixed fifo timout handling. error now in data ready interrupt	2022-11-05 13:34:24 -07:00
Kip Macsai-Goren	23268d22e5	fixed broken instructions so make works.	2022-11-03 23:06:20 +00:00
Ross Thompson	f81d1e15b6	More outline for uart timeout interrupt.	2022-10-28 13:53:56 -05:00
Ross Thompson	372b9890ef	Untested change to uart test for outline of how to handle rx fifo timeout.	2022-10-28 13:31:16 -05:00
Kip Macsai-Goren	d4dd2dcc08	Added test for UART FIFO timeout. Does not pass regression	2022-10-25 05:35:56 +00:00
Kip Macsai-Goren	d5cd67cf09	fixed endianness mstatush problem, passes make, not regression	2022-10-04 17:37:39 +00:00
Kip Macsai-Goren	0d2fcaeab1	added xlen and endianness test edits. xlen passes but endinanness still won't make	2022-09-26 05:03:19 +00:00
Kip Macsai-Goren	3f4c825a1a	added mstatus uxl, sxl bit tests (not tested in regression yet)	2022-09-18 00:11:29 +00:00
Kip Macsai-Goren	dda3b2d383	ported endianness tests to 32 bits (not tested in regression yet)	2022-09-18 00:10:29 +00:00
Kip Macsai-Goren	99596fac84	Fixed typos in existing endianness test	2022-09-18 00:09:52 +00:00
Kip Macsai-Goren	657e19df08	added full coverage of subword loads and stores to endianness test	2022-09-17 23:14:38 +00:00
Kip Macsai-Goren	a4fc5d3476	Created initial endianness tests	2022-09-16 01:06:26 +00:00
David Harris	8b8f045491	Completed PLIC-S tests. Regression working. This completes peripheral tests.	2022-08-03 09:33:56 -07:00
David Harris	62252c2167	Debugging plic-s test	2022-08-03 13:21:09 +00:00
David Harris	6ee8036ae7	plic-s debug	2022-08-03 12:33:09 +00:00
David Harris	e3ea86f984	Started plic-s tests	2022-08-03 03:48:08 +00:00
David Harris	d2de84a456	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
David Harris	763a6d7340	Fixed UART reference output	2022-07-27 22:16:38 +00:00
David Harris	f61f0645fe	Finished UART test	2022-07-27 04:06:59 +00:00
slmnemo	a32698811d	Updated reference file for UART test	2022-07-26 09:39:31 -07:00
slmnemo	528dfd9170	Committing changes made to UART test	2022-07-26 09:14:40 -07:00
slmnemo	5b71ceac5c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-22 17:13:38 -07:00
slmnemo	0bfc3fda1b	Fixed UART FIFO bugs and added FIFO tests	2022-07-22 17:13:19 -07:00
Daniel Torres	e02c67ed5e	fixed 32priv tests, now passing	2022-07-22 15:35:20 -07:00
Daniel Torres	d95b266d49	changes to test.vh for compatability	2022-07-22 15:00:48 -07:00
Daniel Torres	2bbfd67082	added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail	2022-07-22 14:58:55 -07:00
slmnemo	840c40a7ab	UART updates and PMA fix	2022-07-22 14:49:03 -07:00
slmnemo	6d8988f71f	Added test comments to reference output	2022-07-22 12:35:59 -07:00
Daniel Torres	5d7171f6f8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 11:16:09 -07:00
Daniel Torres	526f70e772	commiting current changes to riscof wally tests	2022-07-22 11:14:04 -07:00
slmnemo	12c92a05ff	Added new PLIC and UART tests	2022-07-22 07:12:55 -07:00
slmnemo	49565f944c	Added PLIC and UART tests and new functions to the test library	2022-07-22 07:10:39 -07:00
slmnemo	77f7b179ee	fixed GPIO test by adding a new function to clear PLIC interrupts	2022-07-19 08:59:16 -07:00
slmnemo	43549b10fb	Fixed error in gpio test	2022-07-08 02:27:16 -07:00
Katherine Parry	0b40f38f02	added load and store test	2022-07-07 21:48:51 +00:00
slmnemo	f8059e9e40	Resolved conflicts between different gpio files	2022-07-05 18:38:52 -07:00
slmnemo	b3cd9de9e8	Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.	2022-07-05 18:21:17 -07:00
David Harris	0232593e88	Fixed typos in gpio test comments	2022-07-05 04:57:42 +00:00
David Harris	c830a0baf8	fixed tininess detection in TestFloat examples, merged change in WALLY-TEST-LIB	2022-07-04 03:21:04 +00:00
slmnemo	5ef1266d76	Added termination line to CLINT test	2022-06-27 20:16:29 -07:00
slmnemo	448c9fdbb9	Add CLINT tests from book	2022-06-27 20:09:58 -07:00
slmnemo	ee8349e832	will this work in git	2022-06-27 18:59:44 -07:00
slmnemo	ddf757078b	Added reset read testcodes to GPIO	2022-06-27 18:56:35 -07:00
slmnemo	4c8f5fbd89	Fixed error in GPIO signature	2022-06-23 14:12:28 -07:00
David Harris	66b148b76e	GPIO tests	2022-06-23 21:06:11 +00:00
slmnemo	3d794742e9	Updating new GPIO tests	2022-06-23 13:22:00 -07:00
slmnemo	95b22244ad	Fixed wally-periph, regression is now working	2022-06-23 13:08:15 -07:00
slmnemo	2b2760f5bd	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-06-21 02:16:26 -07:00
slmnemo	2b2ddbcc5e	Added rudimentary GPIO test according to testplans in chapter 15	2022-06-21 02:16:21 -07:00