Ross Thompson
a1c26a16d6
Cleaned up the linux testbench by removing old code and signals.
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Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
2021-08-13 14:39:05 -05:00
Ross Thompson
467e24c05c
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
20a04d8cee
Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the
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cache's SRAM would occur. Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
2021-08-08 11:42:10 -05:00
Ross Thompson
25533bdc49
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
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Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
839822d3b1
Now past the CLINT issues.
2021-08-06 16:16:39 -05:00
Ross Thompson
e1319a2fbe
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
2021-08-06 16:06:50 -05:00
Ross Thompson
d430659983
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Ross Thompson
cd8a66353c
Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.
2021-07-30 14:24:50 -05:00
Ross Thompson
ef66cdeecf
Moved the test bench modules to a common directory.
2021-07-30 14:16:14 -05:00
Ross Thompson
32ec457e09
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
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In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Ross Thompson
007812dbdc
Moved the ReadDataW register into the datapath.
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The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
89e22bc5e8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-22 10:38:24 -05:00
Ross Thompson
e907d57340
Tested all numbers of ways for dcache 1, 2, 4, and 8.
2021-07-22 10:38:07 -05:00
bbracker
9dcd5d3622
fix UART RX FIFO bug where tail pointer can overtake head pointer
2021-07-22 02:09:41 -04:00
bbracker
cdcf419147
make address translator signals visible in waveview
2021-07-21 20:07:49 -04:00
Ross Thompson
511c36fb1b
Improved address bus names and usages in the walker, dcache, and tlbs.
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Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
39fc9278ba
Fixed remaining bugs in 2 way set associative dcache.
2021-07-21 10:35:23 -05:00
Ross Thompson
8d0a552b5b
Partially working 2 way set associative d cache.
2021-07-20 17:51:42 -05:00
bbracker
bb2e3b1e02
remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux
2021-07-19 16:22:05 -04:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
Ross Thompson
5754b5f25f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-19 12:32:35 -05:00
Ross Thompson
2ee97efb9c
Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
2021-07-19 12:32:16 -05:00
bbracker
2702064dda
change buildroot expectations to match reality
2021-07-19 13:20:53 -04:00
Ross Thompson
6ccbdc372d
Broken.
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Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
bbracker
64a81941ff
change memread testvectors to not left-shift bytes and half-words
2021-07-18 21:49:53 -04:00
bbracker
f4f3ef0307
linux testbench progress
2021-07-18 18:47:40 -04:00
Katherine Parry
3527620c0b
fdivsqrt inegrated, but not completley working
2021-07-18 14:03:37 -04:00
bbracker
d85da77069
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-17 14:46:38 -04:00
bbracker
ac908bc2e4
swapped out linux testbench signal names
2021-07-17 14:46:18 -04:00
David Harris
9741b01465
hptw: minor cleanup
2021-07-17 13:40:12 -04:00
Ross Thompson
abce241f68
Also changed the shadow ram's dcache copy widths.
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Merge branch 'dcache' into main
2021-07-16 14:21:09 -05:00
Ross Thompson
bebc7cc5e3
Updated wave file.
2021-07-16 12:34:37 -05:00
Ross Thompson
d3715acf2d
Fixed walker fault interaction with dcache.
2021-07-16 12:22:13 -05:00
bbracker
d38109bc1c
changed stop of linux boot from arch_cpu_idle to do_idle
2021-07-16 12:27:15 -04:00
Ross Thompson
96aa106852
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
5fb5ac3d5a
Updated wave file.
2021-07-15 11:04:49 -05:00
Ross Thompson
f234875779
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
2021-07-14 23:08:07 -05:00
Ross Thompson
6163629204
Finally have the ptw correctly walking through the dcache to update the itlb.
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Still not working fully.
2021-07-14 22:26:07 -05:00
Katherine Parry
701ea38964
Fixed lint warning
2021-07-14 21:24:48 -04:00
Ross Thompson
d3a1a2c90a
Fixed d cache not honoring StallW for uncache writes and reads.
2021-07-14 17:23:28 -05:00
Ross Thompson
771c7ff130
Routed CommittedM and PendingInterruptM through the lsu arb.
2021-07-14 16:18:09 -05:00
Ross Thompson
ef598d0e79
Implemented uncached reads.
2021-07-13 23:03:09 -05:00
Ross Thompson
278bbfbe3c
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Ross Thompson
b780e471b4
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
2021-07-13 14:51:42 -05:00
Ross Thompson
51249a0e04
Fixed the fetch buffer accidental overwrite on eviction.
2021-07-13 14:21:29 -05:00
Ross Thompson
2034a6584f
Dcache AHB address generation was wrong. Needed to zero the offset.
2021-07-13 14:19:04 -05:00
Ross Thompson
ee09fa5f58
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
David Harris
516b710db6
Fixed busybear by restoring InstrValidW needed by testbench
2021-07-13 14:17:36 -04:00
Katherine Parry
acdd2e4504
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
