6 Commits

Author	SHA1	Message	Date
Ross Thompson	9a93193d6a	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Ross Thompson	a8cd4f2b2e	Fixed forwarding around the 2 bit predictor.	2021-03-04 13:01:41 -06:00
Ross Thompson	d0223da2f7	Converted to using the BTB to predict the instruction class.	2021-03-04 09:23:35 -06:00
Ross Thompson	7d6093b302	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. ... About 149307ns of simulation run.	2021-02-18 21:32:15 -06:00
Ross Thompson	bbe0db3ebe	Integrated the branch predictor into the hardward. Not yet working.	2021-02-17 22:19:17 -06:00
Ross Thompson	ca546beaf8	We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. ... This is not yet tested but the system verilog does compile.	2021-02-15 14:51:39 -06:00