Ross Thompson
3e57c899a2
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Abe
9f9b38db9f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 18:22:36 -04:00
Kip Macsai-Goren
9d83566637
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 17:41:47 -04:00
James E. Stine
46001fef27
mod 2 of fpdivsqrt update
2021-07-13 16:59:17 -04:00
James E. Stine
8382a17969
Update fpdivsqrt item until move into uarch
2021-07-13 16:53:20 -04:00
bbracker
f2bf4920d7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 16:16:04 -04:00
bbracker
64d22753b5
changed QEMU to use different ports
2021-07-13 16:15:51 -04:00
Ross Thompson
baa2b5d15f
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399
Fixed the fetch buffer accidental overwrite on eviction.
2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf
Dcache AHB address generation was wrong. Needed to zero the offset.
2021-07-13 14:19:04 -05:00
Ross Thompson
afc1bc9c38
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
David Harris
9de97c1e20
Fixed busybear by restoring InstrValidW needed by testbench
2021-07-13 14:17:36 -04:00
Ross Thompson
47e16f5629
Fixed back to back store issue.
...
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
Abe
46e1a008c3
Downloaded clean version of Coremark from EEMBC github page with which to benchmark RISCV-Wally
2021-07-13 13:37:40 -04:00
David Harris
2ba82d1a5c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 13:26:51 -04:00
David Harris
223086ac33
added or.sv
2021-07-13 13:26:40 -04:00
Katherine Parry
ca19b2e215
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
93d6688c3c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 13:19:24 -04:00
David Harris
b5dddec858
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
bbracker
3565580f40
updated buildroot make procedure to incorporate configs more robustly
2021-07-13 12:40:14 -04:00
Ross Thompson
224e3b2991
Fixed subword write. subword read should not feed into subword write.
2021-07-13 11:21:44 -05:00
Ross Thompson
30b7c4436c
restored rv64ic config back to full sized dtim.
2021-07-13 11:18:54 -05:00
Ross Thompson
3951eb56f5
Modularized the shadow memory to reduce performance hit.
2021-07-13 10:55:57 -05:00
Ross Thompson
e594eb540d
Got the shadow ram cache flush working.
2021-07-13 10:03:47 -05:00
bbracker
99587f58f7
whoops I accidentally made main.config into a symbolic link; now it is a source file
2021-07-13 11:00:01 -04:00
bbracker
fab906821a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 10:04:13 -04:00
bbracker
4b615c1564
working config for a buildroot that boots
2021-07-13 10:04:09 -04:00
David Harris
861ef5e1cb
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
2021-07-13 09:32:02 -04:00
Ross Thompson
49f6eec579
Team work on solving the dcache data inconsistency problem.
2021-07-12 23:46:32 -05:00
Ross Thompson
ecc9b5006e
Now updates the dtim with the dirty data in the dcache.
...
Simulation is showing issues. It lookslike the cache is not
evicting the correct data.
2021-07-12 15:13:27 -05:00
Ross Thompson
1cc258ade1
Progress towards the test bench flush.
2021-07-12 14:22:13 -05:00
Katherine Parry
f3ac46df86
fcvt.sv cleanup
2021-07-11 21:30:01 -04:00
Katherine Parry
36f59f3c99
Almost all convert instructions pass Imperas tests
2021-07-11 18:06:33 -04:00
bbracker
6bd0ca673c
rootfs.cpio no longer overlaps
2021-07-11 05:11:12 -04:00
Ross Thompson
f26d635614
Fixed the spurious AHB requests to address 0. Somehow by not having a default
...
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
2021-07-10 22:34:47 -05:00
Ross Thompson
fed7042fd9
Loads are working.
...
There is a bug when the icache stalls 1 cycle before the d cache.
2021-07-10 22:15:44 -05:00
Ross Thompson
60ed023734
Actually writes the correct data now on stores.
2021-07-10 17:48:47 -05:00
Ross Thompson
efe37ea079
Write miss with eviction works.
2021-07-10 15:17:40 -05:00
Ross Thompson
d65c01bc29
Write Hits and Write Misses without eviction are working correctly! The next
...
step is to add eviction of dirty lines.
2021-07-10 10:56:25 -05:00
bbracker
feaeeaf6ac
greatly stripped down unused stuff in linux config
2021-07-10 11:53:35 -04:00
David Harris
20f2a4e47c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 19:18:35 -04:00
David Harris
d3ab6b192a
added missing tlbmixer.sv
2021-07-09 19:18:23 -04:00
bbracker
3be73695e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 18:56:28 -04:00
bbracker
2a54f6f242
fix_mem.py bugfix
2021-07-09 18:56:17 -04:00
Ross Thompson
b1ceeb40df
Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.
...
I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
2021-07-09 17:14:54 -05:00
bbracker
1f52a2f938
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
Ross Thompson
4c0cee1c19
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
Ross Thompson
ec80cc1820
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
Kip Macsai-Goren
0dff489de2
comment clean up to match textbook chapter
2021-07-09 12:54:09 -04:00
