Ross Thompson
b5a85b55f1
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
ce7e1073fa
Success we've replaced TrapM with FlushD in the IFU.
2022-12-22 21:36:49 -06:00
Ross Thompson
942acb354e
Closing in on icache flushed by FlushD rather than TrapM.
2022-12-22 20:19:09 -06:00
Ross Thompson
47d61984ad
First pass at resolving ifu flush on trap rather than FlushD.
2022-12-22 15:53:06 -06:00
Ross Thompson
0cb2cf9a5b
Changed GatedStallF to GatedStallD.
2022-12-21 16:12:55 -06:00
Ross Thompson
2b1e9f8bed
The optimzied PC+2/4 logic still hanges on wally32priv.
2022-12-21 09:19:34 -06:00
Ross Thompson
a2329c8e9d
Renamed PCPlusUpperF to PCPlus4F.
2022-12-21 09:18:30 -06:00
Ross Thompson
3fc121ef70
Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
...
Switched to even simplier PC+2/4 logic.
2022-12-21 09:00:09 -06:00
Ross Thompson
bc5d5e902a
Comments about PC+2/4.
2022-12-21 08:35:43 -06:00
Ross Thompson
6152c028db
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 18:09:37 -06:00
Ross Thompson
cba2ed64e5
Moved privileged pc logic into privileged unit.
2022-12-20 17:55:45 -06:00
David Harris
07dc11a508
IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
2022-12-20 15:38:30 -08:00
Ross Thompson
b4bdf446cc
Implement FENCE.I as NOP when ZIFENCEI is not supported.
2022-12-20 17:34:11 -06:00
Ross Thompson
637df763ca
Renumbered bits for PCPlusUpper.
2022-12-20 16:33:49 -06:00
Ross Thompson
d35fc5e2a6
Reorganized IFU PCNextF logic.
2022-12-20 12:58:54 -06:00
Ross Thompson
d18ef45c18
More bp/ifu pcmux cleanup.
2022-12-19 23:16:58 -06:00
Ross Thompson
761cf54dcc
Moved more muxes inside bp.
2022-12-19 22:51:55 -06:00
Ross Thompson
0097c166d6
Begin cleanup of ifu. partial move of pc muxes inside bp.
2022-12-19 22:46:11 -06:00
David Harris
2393915bf2
Simplified InstrRawD register
2022-12-19 15:18:42 -08:00
Ross Thompson
c253b882be
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
2022-12-15 09:53:35 -06:00
Ross Thompson
dbc3dac03d
Removed unused flushf.
2022-12-11 16:28:11 -06:00
Ross Thompson
ad7dd56180
Renamed CPUBusy to GatedStallF in IFU.
2022-12-11 15:54:19 -06:00
Ross Thompson
6d573b32d2
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
f09b9e1572
Finished merge of kip and ross's ifu fix.
2022-12-09 16:52:22 -06:00
Ross Thompson
981ac3963a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-09 16:42:16 -06:00
Kip Macsai-Goren
055ca9ee37
Addded fix for 32 bit periph test and added test to regression
2022-12-06 09:56:08 -08:00
Ross Thompson
5dbcf8fb10
Fixed bug Kip found.
...
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
2022-12-06 10:37:45 -06:00
Ross Thompson
faa13a96e0
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
2022-11-16 15:38:37 -06:00
Ross Thompson
b53f8eceef
Renamed Flush to FlushStage in the cache.
2022-11-14 14:11:05 -06:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
54544ae251
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
Ross Thompson
2c5847b01f
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
65c2fe294a
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
Ross Thompson
6ff4abd4f7
Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
2022-10-05 15:46:53 -05:00
Ross Thompson
52a1d3dafe
Name clarifications.
2022-10-05 15:36:56 -05:00
Ross Thompson
98521d073f
Possibly have working dtim + bus config.
2022-10-05 15:08:20 -05:00
Ross Thompson
cabcb5e89e
Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
...
Don't use this commit as the rv32i tests are not passing.
2022-10-05 14:51:02 -05:00
Ross Thompson
41ab4850e1
Disable IFU bus access on TrapM.
2022-10-01 14:54:16 -05:00
Ross Thompson
32449dfe97
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
99e01dd31f
Cleaned up the IFU and LSU around dtim and irom address calculation.
2022-09-21 18:23:56 -05:00
Ross Thompson
f57b0b9950
Updated IROMAdr logic.
2022-09-21 12:42:43 -05:00
Ross Thompson
980b35d585
Merge branch 'tempMain' into main
2022-09-20 13:57:38 -05:00
Ross Thompson
426ec6222b
Added chip enables to sram.
2022-09-20 10:49:14 -05:00
Ross Thompson
bcca9a62c5
Fixed up IFU ahb interface names and widths.
2022-09-19 10:54:22 -05:00
