12 Commits

Author	SHA1	Message	Date
Jordan Carlin	ef778da98d	Eliminate more logical operators and replace with bitwise	2024-05-15 10:50:23 -07:00
David Harris	2580d37fc0	ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder	2024-03-10 22:03:57 -07:00
KelvinTr	01c45ab9d7	Fixed K extension changes	2024-02-28 17:05:08 -06:00
David Harris	74b242ce5c	Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow	2024-01-17 12:25:06 -08:00
David Harris	da4eca4854	Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.	2024-01-15 13:24:57 -08:00
David Harris	9eb6d9c8b8	Added Zicond support	2024-01-11 07:37:15 -08:00
David Harris	001d3cfdc5	Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder	2023-07-02 13:29:27 -07:00
Ross Thompson	4428babda9	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
David Harris	45ee4c2f9f	Added BMU instructions to instruction name decoder	2023-06-15 09:26:09 -07:00
Ross Thompson	1ceea51d8b	Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.	2023-05-31 16:51:00 -05:00
David Harris	9d83749ca6	moved riscvassertons to its own file, added proper license headers to testbench support files	2023-02-16 19:40:27 -08:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00