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Author SHA1 Message Date
David Harris
c06a7e2bbd Replaced build-coremark.sh with Makefile 2021-11-18 20:46:59 -08:00
David Harris
7bdd9b2860 exe2memfile don't print when only 1 file 2021-11-18 20:37:53 -08:00
David Harris
c45f276f86 Moved exe2memfile.pl 2021-11-18 20:32:13 -08:00
David Harris
069ea52ac0 CoreMark cleanup 2021-11-18 20:23:55 -08:00
David Harris
d243f4bcd1 Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca vert "Simplifying riscv-coremark" 
This reverts commit bdc212cf88.
 2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
f2cf09dd76 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-18 16:14:42 -08:00
David Harris
b996598b37 CoreMark testing 2021-11-18 16:14:25 -08:00
slmnemo
870549c01a Removed .* from hazard hzu(.*). 2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
slmnemo
fed613dc72 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:38:51 -08:00
slmnemo
f4380faa4e removed .* from muldiv.sv (REAL) 2021-11-17 13:37:50 -08:00
David Harris
b49c419d0b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:28:33 -08:00
Noah Limpert
0ccc7d5fe8 ieu variable naming changed for clarity 2021-11-17 13:24:28 -08:00
slmnemo
9fb26d5a61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:23:20 -08:00
slmnemo
573f8b0c42 Removed .*s from muldiv.sv 2021-11-17 13:23:12 -08:00
Noah Limpert
ed2285b8e7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:04:33 -08:00
Noah Limpert
832b23b8a4 Updated IFU variable naming for clarity 2021-11-17 12:39:05 -08:00
Kevin Kim
d4e9376854 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 12:18:25 -08:00
Kevin Kim
34b3cc1c8d root level makefile added 2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
3f76549a7d renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
Ross Thompson
3b8bdc7b2d Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. 2021-11-17 12:47:19 -06:00
slmnemo
39983ab2c6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 10:39:52 -08:00
slmnemo
3b4c14e048 Removed .* from muldiv. 2021-11-17 10:39:18 -08:00
Ross Thompson
11a21899d5 Fixed uart by reversing the bit order on transmit. 
Set prescale to 0.
 2021-11-17 10:32:41 -06:00
Skylar Litz
e35faa9b8a fixed interrupt timing bug 2021-11-16 16:46:17 -08:00
davidharrishmc
984a7a6ccd Update README.md 
updated linux_testvectors path
 2021-11-16 12:33:47 -08:00
David Harris
5a521e28ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
23bd24323b get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
Ross Thompson
4af7a27d87 Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing. 2021-11-12 17:37:07 -06:00
Ross Thompson
b8572d6a2a Changed several things. 
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
 2021-11-12 11:13:50 -06:00
Skylar Litz
99a15e7897 fix timing of delayed interrupt 2021-11-11 09:35:51 -08:00
David Harris
f96152fa31 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
kipmacsaigoren
e90d0eee72 fixed small errors causing overwrites in timing reports 2021-11-10 13:01:09 -06:00
Kevin Kim
a7684f1b59 Makefile added in regression directory: 
-cd's into imperas then runs make commands, finally running the tvLinker script
 2021-11-09 10:55:48 -08:00
bbracker
24c5796680 genCheckpoint path bugfix 2021-11-06 15:25:10 -07:00
bbracker
b3288beb38 update README.md to reflect new tvLinker location 2021-11-06 15:02:16 -07:00
bbracker
1597e0dac6 increase expectations for buildroot and timeout count 2021-11-06 14:57:29 -07:00
bbracker
e585a173e5 automated checkpoint generator 2021-11-06 14:37:49 -07:00
bbracker
d0ad8d3ae3 update tvLinker to new shared dir 2021-11-06 14:15:16 -07:00
bbracker
31d38286da make genCheckpoint accept instr count as argument 2021-11-06 14:14:15 -07:00
bbracker
24d3244cfe checkpoint MIDELEG support 2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
3077769cbd checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
kipmacsaigoren
e7b25f7c95 changed number of critical paths reported to 1, added lots of internal signals and new report files. 2021-11-05 11:59:33 -05:00
davidharrishmc
f540bb13c0 fixed 64i 2021-11-03 13:49:07 -07:00
davidharrishmc
099c4e8b6b fixed 64i 2021-11-03 13:40:23 -07:00
davidharrishmc
d957d86f3b added wally-riscv-arch-test compile commands 2021-11-03 13:30:21 -07:00
Kevin
b34569c358 changed code aligner to run recursively on a root directory 
-only runs the aligner on .sv files
-runs recursively on sub-directories
 2021-11-03 10:49:34 -07:00