1698 Commits

Author	SHA1	Message	Date
bbracker	42ba205c4f	automatic bug finder script	2021-11-19 20:25:00 -08:00
slmnemo	870549c01a	Removed .* from hazard hzu(.*).	2021-11-17 14:21:23 -08:00
slmnemo	a98dcd11ee	Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.	2021-11-17 14:08:08 -08:00
slmnemo	fed613dc72	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-11-17 13:38:51 -08:00
slmnemo	f4380faa4e	removed .* from muldiv.sv (REAL)	2021-11-17 13:37:50 -08:00
Noah Limpert	0ccc7d5fe8	ieu variable naming changed for clarity	2021-11-17 13:24:28 -08:00
slmnemo	9fb26d5a61	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-11-17 13:23:20 -08:00
slmnemo	573f8b0c42	Removed .*s from muldiv.sv	2021-11-17 13:23:12 -08:00
Noah Limpert	ed2285b8e7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-11-17 13:04:33 -08:00
Noah Limpert	832b23b8a4	Updated IFU variable naming for clarity	2021-11-17 12:39:05 -08:00
Kevin Kim	d4e9376854	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-11-17 12:18:25 -08:00
Kevin Kim	34b3cc1c8d	root level makefile added	2021-11-17 12:17:56 -08:00
Kip Macsai-Goren	3f76549a7d	renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv	2021-11-17 10:53:17 -08:00
Skylar Litz	e35faa9b8a	fixed interrupt timing bug	2021-11-16 16:46:17 -08:00
bbracker	23bd24323b	get current privilege level from GDB for checkpoints	2021-11-15 14:49:00 -08:00
Skylar Litz	99a15e7897	fix timing of delayed interrupt	2021-11-11 09:35:51 -08:00
Kevin Kim	a7684f1b59	Makefile added in regression directory: ... -cd's into imperas then runs make commands, finally running the tvLinker script	2021-11-09 10:55:48 -08:00
bbracker	1597e0dac6	increase expectations for buildroot and timeout count	2021-11-06 14:57:29 -07:00
bbracker	24d3244cfe	checkpoint MIDELEG support	2021-11-06 03:44:23 -07:00
bbracker	1d3d7cbe1e	fix merge conflict	2021-11-05 23:42:15 -07:00
bbracker	3077769cbd	checkpoints now use binary ram files	2021-11-05 22:37:05 -07:00
Kevin	b34569c358	changed code aligner to run recursively on a root directory ... -only runs the aligner on .sv files -runs recursively on sub-directories	2021-11-03 10:49:34 -07:00
bbracker	e4cf044932	fix testbench interrupt timing	2021-11-02 21:19:12 -07:00
bbracker	8563c0f016	linux testgen refactor	2021-11-01 14:09:49 -07:00
David Harris	910957704b	Add3d wally32i test	2021-11-01 13:17:49 -07:00
David Harris	4b57af9cff	PIPELINE test running	2021-11-01 12:44:35 -07:00
David Harris	c306884e2c	Adding custom Wally test infrastructure	2021-11-01 08:48:46 -07:00
bbracker	38d26e857b	fix buildroot graphical sim	2021-10-31 18:33:43 -07:00
David Harris	e9244e7a85	Fixed exe2memfile parsing of weird line in arch64d test	2021-10-30 07:26:18 -07:00
David Harris	f35b31f166	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-29 22:32:08 -07:00
David Harris	717f9d48e9	tesgen cleanup, added riscv-arch-test D tests	2021-10-29 22:31:48 -07:00
David Harris	f7acd31bcb	rearranging testgen	2021-10-29 22:28:37 -07:00
Ross Thompson	8aad95366d	Fixed the 4 way set associative pseudo LRU replacement policy.	2021-10-29 12:46:02 -05:00
Ross Thompson	f61fcd25a9	Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.	2021-10-29 11:03:37 -05:00
Ross Thompson	54c714d222	Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.	2021-10-28 11:07:18 -05:00
bbracker	fe2bf13720	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-27 14:40:31 -07:00
bbracker	d14fa074ec	checkpoint generator off-by-one error fix	2021-10-27 14:10:29 -07:00
Noah Limpert	21ea270fe2	Have replaced .* with signal names in ifu	2021-10-27 13:45:37 -07:00
koooo142857	0a33b0904d	aligned all files in ifu folder	2021-10-27 12:43:55 -07:00
David Harris	e62b57e2c2	commented out some failing FPU tests	2021-10-27 11:27:34 -07:00
David Harris	9cfb8deaab	Fixed FResultSelM to select proper flags	2021-10-27 11:02:42 -07:00
David Harris	31a2346c37	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-27 10:37:46 -07:00
David Harris	0421b7af56	Changes for floating point sims	2021-10-27 10:37:35 -07:00
Ross Thompson	fed8882aec	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-27 09:59:55 -05:00
Ross Thompson	d98baf90a3	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
bbracker	52529db40b	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-26 12:43:48 -07:00
bbracker	1409dc48a8	bugfix argument passing to GDB script; remove outdated GDB script	2021-10-26 12:43:42 -07:00
David Harris	f793dd7a5e	removed unused signal from wave.do	2021-10-26 09:02:22 -07:00
David Harris	7d516c65e7	commented out nonworking tests	2021-10-26 08:56:49 -07:00
David Harris	ca700610f8	removed referenc outputs	2021-10-26 08:51:49 -07:00