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Author SHA1 Message Date
Ross Thompson
9849983348 At long last found the subtle bug in the LRU. 
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
 2022-12-17 10:03:08 -06:00
Ross Thompson
c985988867 Fixed a bug with the new cache flush changes. 2022-12-16 19:28:32 -06:00
Ross Thompson
9b9e954cc5 Cleanup comments. 2022-12-16 17:08:35 -06:00
Ross Thompson
5f556817c7 Further cleanfsm cleanup. 2022-12-16 16:37:45 -06:00
Ross Thompson
493b1a4280 More cachefsm cache flush cleanup. 2022-12-16 16:32:21 -06:00
Ross Thompson
3132246a46 Oups found a bug with the new flush cache states. 2022-12-16 16:22:40 -06:00
Ross Thompson
698ca7d482 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 15:37:03 -06:00
Ross Thompson
91e64a0d67 Cleanup of cache flush fsm enhancement. 2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7 Rough draft of cache flush fsm enhancement. 2022-12-16 15:28:22 -06:00
cturek
0ceecd9961 Added integer support for initC 2022-12-16 19:02:11 +00:00
Ross Thompson
9c67972b21 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-16 12:52:22 -06:00
Ross Thompson
f04ca5cb6a Fixed regression-wally to correct remove and mkdir wkdir. 2022-12-16 12:51:21 -06:00
cturek
9340a5eb49 Added mux for integer special case, renamed signals to match pipelined stage 2022-12-16 18:43:49 +00:00
David Harris
940fd2f924 Clean up interrupt masking by Commit 2022-12-16 08:27:39 -08:00
David Harris
a285f289a6 Disabled starting FPU divider when IDIV_ON_FPU = 0 2022-12-16 06:35:29 -08:00
cturek
9f1aa7ad19 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-16 03:41:39 +00:00
Ross Thompson
3ee6ed8542 Updated fpga constraints 2022-12-15 16:45:55 -06:00
David Harris
da2d68c699 Use FlushE to reset integer divider FSM 2022-12-15 11:00:54 -08:00
David Harris
a8126458f6 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
97a432570a Regression delete wkdir files to prevent spurious failures 2022-12-15 10:24:58 -08:00
David Harris
3bef12b108 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
Ross Thompson
8cd6a74c8f Hazard cleanup. 2022-12-15 10:05:17 -06:00
Ross Thompson
c253b882be Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
Ross Thompson
0358a8d255 Merge branch 'main' into hazards 2022-12-15 08:44:59 -06:00
David Harris
e80e84aace Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
David Harris
643a2e7cf9 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
cturek
482caec42d Fixed BZero and initU/initUM muxes 2022-12-14 16:44:46 +00:00
Ross Thompson
4a0e4aed99 Signal renames to reflect figures. 2022-12-14 09:49:15 -06:00
Ross Thompson
8f04f2d9e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-14 09:34:34 -06:00
Ross Thompson
b69aa39f30 Reduced complexity of linebytemask. 2022-12-14 09:34:29 -06:00
cturek
e4c1bb2bff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-12-14 15:13:44 +00:00
Ross Thompson
0f0fed2496 Broken dont' use. 2022-12-11 23:24:01 -06:00
Ross Thompson
dbc3dac03d Removed unused flushf. 2022-12-11 16:28:11 -06:00
Ross Thompson
ad7dd56180 Renamed CPUBusy to GatedStallF in IFU. 2022-12-11 15:54:19 -06:00
Ross Thompson
5b38b4e639 Renamed CPUBusy in LSU. 2022-12-11 15:52:51 -06:00
Ross Thompson
6d573b32d2 Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1 Renamed CPUBusy to Stall in cache. 2022-12-11 15:49:34 -06:00
Ross Thompson
a58fbd618e Moved CPUBusy out of HPTW. 2022-12-11 15:48:00 -06:00
cturek
930fcbe956 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs 2022-12-10 21:56:35 +00:00
Ross Thompson
d3b2e331c2 Added comments about why it is not possible to use FlushWay and VictimWay directly. 2022-12-09 17:07:35 -06:00
Ross Thompson
f09b9e1572 Finished merge of kip and ross's ifu fix. 2022-12-09 16:52:22 -06:00
Ross Thompson
981ac3963a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-09 16:42:16 -06:00
Ross Thompson
1a24e7029f Minor simplification of cacheway way selection muxes. 2022-12-09 16:42:05 -06:00
Kip Macsai-Goren
055ca9ee37 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Ross Thompson
9dd0d66ab5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-06 10:38:14 -06:00
Ross Thompson
5dbcf8fb10 Fixed bug Kip found. 
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
 2022-12-06 10:37:45 -06:00
Kip Macsai-Goren
55627f40e2 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00
Kip Macsai-Goren
c6662933c4 commented out periph test from wally32 periph so rv32ic doesn't hang 2022-12-05 20:23:16 -08:00
Kip Macsai-Goren
4c81b6fa5f added corrrect scr read out of uart to periph test 2022-12-05 20:16:02 -08:00
Kip Macsai-Goren
4e2f4855e6 added passing tests to regression 2022-12-05 20:16:02 -08:00