1626 Commits

Author	SHA1	Message	Date
David Harris	da2d68c699	Use FlushE to reset integer divider FSM	2022-12-15 11:00:54 -08:00
David Harris	a8126458f6	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
David Harris	97a432570a	Regression delete wkdir files to prevent spurious failures	2022-12-15 10:24:58 -08:00
David Harris	3bef12b108	Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE	2022-12-15 08:23:34 -08:00
Ross Thompson	8cd6a74c8f	Hazard cleanup.	2022-12-15 10:05:17 -06:00
Ross Thompson	c253b882be	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
Ross Thompson	0358a8d255	Merge branch 'main' into hazards	2022-12-15 08:44:59 -06:00
David Harris	e80e84aace	Added IDIV_ON_FPU flag to control whether integer division uses FPU	2022-12-15 06:37:55 -08:00
David Harris	643a2e7cf9	Use FPU divider for integer division when F is supported	2022-12-14 17:03:13 -08:00
Ross Thompson	4a0e4aed99	Signal renames to reflect figures.	2022-12-14 09:49:15 -06:00
Ross Thompson	8f04f2d9e7	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-12-14 09:34:34 -06:00
Ross Thompson	b69aa39f30	Reduced complexity of linebytemask.	2022-12-14 09:34:29 -06:00
cturek	e4c1bb2bff	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-12-14 15:13:44 +00:00
Ross Thompson	0f0fed2496	Broken dont' use.	2022-12-11 23:24:01 -06:00
Ross Thompson	dbc3dac03d	Removed unused flushf.	2022-12-11 16:28:11 -06:00
Ross Thompson	ad7dd56180	Renamed CPUBusy to GatedStallF in IFU.	2022-12-11 15:54:19 -06:00
Ross Thompson	5b38b4e639	Renamed CPUBusy in LSU.	2022-12-11 15:52:51 -06:00
Ross Thompson	6d573b32d2	Changed CPUBusy to Stall in ebu modules.	2022-12-11 15:51:35 -06:00
Ross Thompson	232f866ad1	Renamed CPUBusy to Stall in cache.	2022-12-11 15:49:34 -06:00
Ross Thompson	a58fbd618e	Moved CPUBusy out of HPTW.	2022-12-11 15:48:00 -06:00
cturek	930fcbe956	Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs	2022-12-10 21:56:35 +00:00
Ross Thompson	d3b2e331c2	Added comments about why it is not possible to use FlushWay and VictimWay directly.	2022-12-09 17:07:35 -06:00
Ross Thompson	f09b9e1572	Finished merge of kip and ross's ifu fix.	2022-12-09 16:52:22 -06:00
Ross Thompson	981ac3963a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-12-09 16:42:16 -06:00
Ross Thompson	1a24e7029f	Minor simplification of cacheway way selection muxes.	2022-12-09 16:42:05 -06:00
Kip Macsai-Goren	055ca9ee37	Addded fix for 32 bit periph test and added test to regression	2022-12-06 09:56:08 -08:00
Ross Thompson	9dd0d66ab5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-12-06 10:38:14 -06:00
Ross Thompson	5dbcf8fb10	Fixed bug Kip found. ... The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.	2022-12-06 10:37:45 -06:00
Kip Macsai-Goren	55627f40e2	added passing GPIO test to 64 bit tests	2022-12-05 21:31:00 -08:00
Kip Macsai-Goren	c6662933c4	commented out periph test from wally32 periph so rv32ic doesn't hang	2022-12-05 20:23:16 -08:00
Kip Macsai-Goren	4e2f4855e6	added passing tests to regression	2022-12-05 20:16:02 -08:00
Kip Macsai-Goren	540d6c2f41	added -01 to all WALLY tests	2022-12-05 20:16:02 -08:00
Ross Thompson	1a9c932157	Renamed SelBusBuffer to SelFetchBuffer.	2022-12-05 17:51:13 -06:00
Ross Thompson	92066f81b6	Removed commented code.	2022-12-05 17:21:56 -06:00
Ross Thompson	37551ecc43	Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.	2022-12-05 17:19:51 -06:00
Ross Thompson	dc31add951	Cache signal renames.	2022-12-04 16:09:09 -06:00
Ross Thompson	9bf0eedf73	Optimized way selection logic.	2022-12-04 12:30:56 -06:00
Ross Thompson	a130a96b45	Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.	2022-12-04 01:20:51 -06:00
Ross Thompson	3dea04e644	Moved selectedway mux into cacheway. It makes way more sense there.	2022-12-04 01:15:47 -06:00
Ross Thompson	f557150cae	Rename LineByteMux to FetchbufferbyteSel.	2022-12-04 01:00:04 -06:00
Ross Thompson	fc05e27416	Updated riscv arch test removed misaligned1.	2022-12-04 00:18:10 +00:00
Ross Thompson	350fdd944d	Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." ... This reverts commit fb221d7b64.	2022-12-04 00:01:58 +00:00
cturek	fb221d7b64	Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.	2022-12-02 21:44:29 +00:00
cturek	04ac350a29	Added flops to preproc	2022-12-02 20:31:08 +00:00
David Harris	3a07d56d33	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
David Harris	1b0f878c16	Renamed DivStartE to IFDivStartE	2022-12-02 11:30:49 -08:00
David Harris	db5f3c15a4	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
David Harris	a86c9de36b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-12-02 04:28:50 -08:00
David Harris	6079a01bc8	update test list	2022-12-02 04:28:47 -08:00
Ross Thompson	602d191580	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-12-01 22:36:07 -06:00