David Harris
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0a067d342f
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Restored missing floating point load/store tests
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2022-12-25 22:28:14 -08:00 |
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Kip Macsai-Goren
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d25d699800
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Ross Thompson
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7a352edf13
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Attempted to make a cache test.
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2022-12-18 17:15:08 -06:00 |
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Ross Thompson
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9d1cb9337e
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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cturek
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930fcbe956
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Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
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2022-12-10 21:56:35 +00:00 |
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Kip Macsai-Goren
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055ca9ee37
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Addded fix for 32 bit periph test and added test to regression
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2022-12-06 09:56:08 -08:00 |
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Kip Macsai-Goren
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55627f40e2
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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c6662933c4
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commented out periph test from wally32 periph so rv32ic doesn't hang
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2022-12-05 20:23:16 -08:00 |
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Kip Macsai-Goren
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4e2f4855e6
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added passing tests to regression
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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540d6c2f41
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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fc05e27416
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Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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David Harris
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db5f3c15a4
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FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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David Harris
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6079a01bc8
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update test list
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2022-12-02 04:28:47 -08:00 |
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David Harris
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0d23ab3ec1
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reorder tests
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2022-12-01 16:27:33 -08:00 |
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David Harris
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3a8602523e
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FPU test list
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2022-12-01 10:18:36 -08:00 |
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cturek
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10c2d45888
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div tests in sim-wally
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2022-11-30 02:32:04 +00:00 |
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Kip Macsai-Goren
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44ea8d8b22
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added failing satp invalid tests to regression
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2022-11-29 10:43:38 -08:00 |
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cturek
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9d30a832c3
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Reoredered tests for arch32m
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2022-11-09 18:42:00 +00:00 |
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David Harris
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53a88fec8f
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Reorder embench tests to prevent crash
|
2022-11-04 15:21:51 -07:00 |
|
Ross Thompson
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a59df0c77d
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Created one off test to replicate the floating point forwarding hazard bug.
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2022-10-22 16:29:12 -05:00 |
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Kip Macsai-Goren
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c18c181fc0
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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Kip Macsai-Goren
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cc7d1c8ef9
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Created initial endianness tests
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2022-09-16 01:06:26 +00:00 |
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Ross Thompson
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3571fb18c2
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Modified regression tests to add some ahb configurations.
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2022-09-07 12:03:58 -05:00 |
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DTowersM
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bdeb5c6509
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fixed qrduino keyerror in embench test
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2022-08-31 00:17:58 +00:00 |
|
Ross Thompson
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fc22e807e2
|
Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
|
2022-08-24 17:52:25 -05:00 |
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Katherine Parry
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9549c23f45
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sqrt tests in regression uncommented and pass
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2022-08-07 23:38:10 +00:00 |
|
David Harris
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898dbc8e74
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
|
David Harris
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7e5b78f240
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
257107f908
|
Partitioned fma into separate files
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2022-08-01 18:07:38 +00:00 |
|
David Harris
|
2d7f4b133c
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
c6a58eb5b6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
|
2022-07-25 16:23:10 -07:00 |
|
Daniel Torres
|
24828db612
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
4198145ce2
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
ba2dcf6da4
|
fixed error in tests.vh
|
2022-07-22 14:55:55 -07:00 |
|
slmnemo
|
ec1ed5bd94
|
Added UART test to peripheral test
|
2022-07-22 14:55:34 -07:00 |
|
Daniel Torres
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574e603d69
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 13:52:19 -07:00 |
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Daniel Torres
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139e657fcc
|
commented out embench test that should be commented out
|
2022-07-22 13:52:13 -07:00 |
|
slmnemo
|
cb16a75119
|
Added PLIC test to regression
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2022-07-22 12:35:37 -07:00 |
|
slmnemo
|
df568fd202
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
|
Daniel Torres
|
8dcb794bbb
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
|
2022-07-21 20:58:58 -07:00 |
|
Daniel Torres
|
a8faddf81f
|
removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
|
2022-07-21 12:47:51 -07:00 |
|
Daniel Torres
|
5b1adc7a67
|
commented out embench 2.0 tests
|
2022-07-19 13:36:18 -07:00 |
|
Katherine Parry
|
18d7fee541
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
|
DTowersM
|
fe7d03a3da
|
added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
|
2022-07-11 21:13:09 +00:00 |
|
Katherine Parry
|
62205ebb3b
|
renamed FLoad2 to FStore2
|
2022-07-09 00:26:45 +00:00 |
|
Katherine Parry
|
97e7e619d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
DTowersM
|
4786fb9fd6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-07 23:11:35 +00:00 |
|
DTowersM
|
aa8580b2dc
|
new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
|
2022-07-07 23:11:02 +00:00 |
|
Katherine Parry
|
75a8cea4e4
|
srt divider merged into fpu
|
2022-07-07 16:01:33 -07:00 |
|
Katherine Parry
|
7771f7b3eb
|
added load and store test
|
2022-07-07 21:48:51 +00:00 |
|