Abe
89dc9ba6e4
Updated riscv64-unknown-elf-gcc location so that it can be easily accessed
2021-07-20 14:18:13 -04:00
bbracker
6b72b1f859
ignore mhpmcounters because QEMU doesn't implement them
2021-07-20 13:37:52 -04:00
Kip Macsai-Goren
93ea2000dc
Updated MMU tests to use shared library in assembly
2021-07-20 12:35:30 -04:00
bbracker
a1ea654b11
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 12:08:46 -04:00
David Harris
e1a1a8395e
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 08:57:13 -04:00
bbracker
077662bfa1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 05:40:49 -04:00
bbracker
9e658466e6
testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
2021-07-20 05:40:39 -04:00
James E. Stine
12e09a7ace
slight mod to fpdiv - still bug in batch vs. non-batch
2021-07-20 01:47:46 -04:00
bbracker
3b10ea9785
major fixes to CSR checking
2021-07-20 00:22:07 -04:00
Ross Thompson
365485bd8b
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
Ross Thompson
508c3e35af
Restored TIM range.
2021-07-19 21:17:31 -05:00
bbracker
99fa2bbbc3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 19:30:40 -04:00
bbracker
cb15d7e4c7
change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)
2021-07-19 19:30:29 -04:00
David Harris
23b76a724d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 18:19:59 -04:00
David Harris
4d40b5faef
Added cache configuration to config files
2021-07-19 18:19:46 -04:00
bbracker
c1d63fe77c
MemRWM shouldn't factor into PCD checking
2021-07-19 18:03:30 -04:00
bbracker
4d10cfc98b
create qemu_output.txt
2021-07-19 18:02:41 -04:00
bbracker
c8203c171e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 17:11:49 -04:00
bbracker
f7d040af1e
make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
2021-07-19 17:11:42 -04:00
Kip Macsai-Goren
5880cbafe4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 16:46:46 -04:00
bbracker
1aeef4e7d1
remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux
2021-07-19 16:22:05 -04:00
bbracker
bc5222e721
put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
2021-07-19 16:19:24 -04:00
bbracker
f17f6cea56
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:42:26 -04:00
bbracker
65df5c087b
adapt testbench to removal of ReadDataWEn signal
2021-07-19 15:42:14 -04:00
bbracker
ae5663a244
adapt testbench to removal of signal
2021-07-19 15:41:50 -04:00
bbracker
64e0fe4c5a
whoops MTIMECMP is always 64 bits
2021-07-19 15:40:53 -04:00
Abe
69c6a7d2cc
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:20:38 -04:00
kipmacsaigoren
5990ed23a4
removed Wally test framwork include statement
2021-07-19 19:15:11 +00:00
bbracker
bdb1ece183
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:13:14 -04:00
bbracker
cd469035be
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
Kip Macsai-Goren
2614df627e
added changes to priority encoders from synthesis branch (correctly this time I hope)
2021-07-19 15:06:14 -04:00
Ross Thompson
bf3ca50a9a
Furture simplification of the dcache ReadDataW update.
2021-07-19 12:46:31 -05:00
Ross Thompson
9f76e1d64d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-19 12:32:35 -05:00
Ross Thompson
b61dad4b83
Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
2021-07-19 12:32:16 -05:00
bbracker
1b0b9d0f79
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 13:21:04 -04:00
bbracker
f31a0ded75
change buildroot expectations to match reality
2021-07-19 13:20:53 -04:00
Kip Macsai-Goren
93820169f1
rename page table levels
2021-07-19 13:00:59 -04:00
Kip Macsai-Goren
3d878ff4c0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 13:00:25 -04:00
Ross Thompson
4d53b9002f
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
bbracker
67eb1f5c6b
change sram1rw to have a small delay so that we don't have signals changing on clock edges
2021-07-19 11:30:07 -04:00
Kip Macsai-Goren
55fc939ac6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 10:56:48 -04:00
Kip Macsai-Goren
ab142300ef
Revert "added priority circuit to attempt to remove delay due to rippling in pmpadrdec"
...
This reverts commit 9461fd9fbd51e17a416a7df6982379fbfa6b0974.
2021-07-19 10:46:17 -04:00
David Harris
2ed6285a3d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 10:34:18 -04:00
Kip Macsai-Goren
e4a9abc16c
added priority circuit to attempt to remove delay due to rippling in pmpadrdec
2021-07-19 10:34:17 -04:00
James Stine
7d571f27a6
delete sbtm_a4 and sbtm_a5 as they are not needed
2021-07-19 08:06:00 -05:00
James Stine
186b5dee69
remove sbtm3.sv - not needed
2021-07-19 08:00:53 -05:00
James Stine
5b1f9797f5
update part I on sbtm change
2021-07-19 07:59:27 -05:00
David Harris
8e01007d1c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 00:25:06 -04:00
Abe
60769388a0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-18 23:09:57 -04:00
Katherine Parry
c9180f4ebd
FDIV and FSQRT passes when simulating in modelsim
2021-07-18 23:00:04 -04:00
