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Configurable RISC-V Processor
1,476 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
c1d63fe77c
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bbracker c1d63fe77c MemRWM shouldn't factor into PCD checking
2021-07-19 18:03:30 -04:00
riscv-coremark
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined MemRWM shouldn't factor into PCD checking 2021-07-19 18:03:30 -04:00
.gitattributes
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
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README.md

riscv-wally

Configurable RISC-V Processor