8 Commits

Author	SHA1	Message	Date
Shreya Sanghai	518618ad38	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	8e51935082	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Thomas Fleming	e57b6cf18c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
Ross Thompson	9a93193d6a	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Thomas Fleming	85dcbee86b	Place tlb parameters into constant header file	2021-03-05 13:35:24 -05:00
Shreya Sanghai	7cd8f1a592	added performance counters	2021-03-04 11:42:52 -05:00
Teo Ene	b9701293a0	Changed TIMBASE in coremark config file	2021-02-25 11:03:41 -06:00
Teo Ene	cfd45a46c3	Added provisional coremark files from work with Elizabeth	2021-02-24 20:07:07 -06:00