Ross Thompson
366a96a0fc
Possible fix for issue 148.
...
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
e03a533775
Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault
2023-03-22 06:29:30 -07:00
David Harris
a1eccf37dc
Fix Issue 145
2023-03-22 04:33:14 -07:00
Ross Thompson
3cae6ca90f
Updated NextAdr to NextSet.
2023-03-13 14:54:13 -05:00
Ross Thompson
ada099c58b
Changes BTA to BPBTA.
2023-03-12 14:36:46 -05:00
Ross Thompson
a5523400ae
Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.
2023-03-12 13:21:22 -05:00
Ross Thompson
a6b851a672
Renamed signals to be consistent with textbook.
2023-03-06 18:29:31 -06:00
Ross Thompson
31fcc0daf7
Renamed PCFSpill to PCSpillF.
2023-03-06 17:50:57 -06:00
Ross Thompson
473ed2b475
Renamed InstrFirstHalf to InstrFirstHalfF.
2023-03-06 17:48:57 -06:00
Ross Thompson
0cb5369351
Renamed BTB misprediction to BTA.
2023-03-03 00:18:34 -06:00
Ross Thompson
aabb454d1c
Added the i and d cache cycle counters.
2023-03-02 23:54:56 -06:00
Ross Thompson
b98e007a53
Cleaned up branch predictor performance counters.
2023-03-01 17:05:42 -06:00
Ross Thompson
90b2f0a652
Set bp to use instruction class prediction by default.
2023-03-01 11:52:42 -06:00
Ross Thompson
dea6b643a6
Branch predictor cleanup.
...
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
2023-03-01 11:24:24 -06:00
Ross Thompson
03a6679ba0
More btb cleanup.
2023-03-01 10:47:00 -06:00
Ross Thompson
554e7d0973
Minor fix to btb.
2023-03-01 10:45:40 -06:00
Ross Thompson
a6917d07f3
Name cleanup.
2023-02-28 17:48:58 -06:00
Ross Thompson
4c0e7f297a
Found the performance bug with the branch predictor btb power saving update.
2023-02-28 15:57:34 -06:00
Ross Thompson
2ebe600f54
Name changes to reflect diagrams.
2023-02-28 15:37:25 -06:00
Ross Thompson
be4823f7dd
Undid the btb update as it reduces performance.
2023-02-28 15:21:56 -06:00
Ross Thompson
9dd3379744
This icpred and btb changes are causing a performance issue.
2023-02-27 20:00:50 -06:00
Ross Thompson
544abe2819
Modified the BTB to save power by not updating when the prediction is unchanged.
2023-02-27 17:37:29 -06:00
Ross Thompson
bc5aecf948
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-27 09:48:03 -06:00
Ross Thompson
318189e5e6
Signal name changes.
2023-02-27 00:39:19 -06:00
Ross Thompson
c89812b2d4
Branch predictor cleanup.
2023-02-26 21:28:36 -06:00
Ross Thompson
e8c5e5b5ff
Create module for instruction class prediction and decoding.
2023-02-26 20:20:30 -06:00
David Harris
21b28fd1bb
Renamed DAPageFault to UpdateDA
2023-02-26 17:51:45 -08:00
Ross Thompson
72be4318b8
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-02-26 12:06:06 -06:00
David Harris
35653a18b7
Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED
2023-02-26 09:38:32 -08:00
Ross Thompson
7f8034013d
PHT was enabled using the wrong ~flush and ~stall.
2023-02-24 22:57:32 -06:00
Ross Thompson
eb9dc7e67d
gshare cleanup.
2023-02-24 22:55:51 -06:00
Ross Thompson
9df05f0b3d
More signal renames.
2023-02-24 19:56:55 -06:00
Ross Thompson
8bd4a4c35b
Renamed signals to match new figures.
2023-02-24 19:51:47 -06:00
Ross Thompson
f95f326b3d
Renamed signals to match figure 10.18.
2023-02-24 19:22:14 -06:00
Ross Thompson
4031b89f18
Possible fix to btb performance issue.
2023-02-24 18:36:41 -06:00
Ross Thompson
ea8cb7dd78
Cleanup.
2023-02-24 18:20:42 -06:00
Ross Thompson
a14dcaa241
Completed critical path gshare fix.
2023-02-24 18:02:00 -06:00
Ross Thompson
31d6531af2
Prep to fix gshare critical path.
2023-02-24 17:54:48 -06:00
Ross Thompson
5db56460b9
Modified btb forwarding logic to reduce critical path.
2023-02-24 17:47:43 -06:00
Ross Thompson
2920179435
Major cleanup of bp.
2023-02-23 16:19:03 -06:00
Ross Thompson
fa49de8391
Partial replacement of InstrClassX with {JalX, RetX, JumpX, and BranchX}.
2023-02-23 15:55:34 -06:00
Ross Thompson
8503982328
Branch predictor cleanup.
2023-02-23 15:15:14 -06:00
Ross Thompson
403b2b7be1
Moved more branch predictor logic into the performance counter block.
2023-02-23 15:14:56 -06:00
Ross Thompson
526f046fb0
Added if generate around bp logic only used with performance counters.
2023-02-23 14:39:31 -06:00
Ross Thompson
2d919fa9e3
Renamed PCPredX to BTAX.
2023-02-23 14:33:32 -06:00
Ross Thompson
c736d7c1f3
Fixed bug in basic gshare.
2023-02-22 12:54:46 -06:00
Ross Thompson
849856034b
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-22 09:11:57 -06:00
Ross Thompson
5dde3af22e
Oups. Turns out dc_shell does not like string parameters.
...
Switched gshare to use an integer parameter to select between gshare and global.
2023-02-22 09:11:46 -06:00
David Harris
f0566173e6
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-02-21 09:58:18 -08:00
