slmnemo
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3626d5880e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:30:33 -07:00 |
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David Harris
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9e1ec0255f
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Removed SRT testvectors from repo
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2022-06-13 19:27:33 +00:00 |
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slmnemo
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05a217c7e7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:27:23 -07:00 |
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slmnemo
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c5d2037a7f
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Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
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2022-06-13 12:26:18 -07:00 |
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slmnemo
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a21d731834
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Added more comments
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2022-06-13 12:26:08 -07:00 |
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David Harris
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9080e35e54
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 19:26:07 +00:00 |
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David Harris
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09d72a33c5
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Fixed XOR logic in GPIO
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2022-06-13 19:26:03 +00:00 |
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slmnemo
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9f4ca06f7f
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Added comment about name of LSUBusInit/Lock signal
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2022-06-13 10:56:02 -07:00 |
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slmnemo
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a79737e95b
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Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
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2022-06-10 20:43:56 -07:00 |
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slmnemo
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d6a1ee1141
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Added comments to signals added so the bus is easier to analyze
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2022-06-10 20:30:04 -07:00 |
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slmnemo
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31852fdb19
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Fixed failed regression state by only enabling counting when doing cached operations
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2022-06-10 20:00:09 -07:00 |
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slmnemo
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0e10435fb6
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Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
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2022-06-10 19:10:01 -07:00 |
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Madeleine Masser-Frye
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032385aee3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-10 21:11:47 +00:00 |
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Madeleine Masser-Frye
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374dfd1fc2
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added 'd' suffix to muxes for data-critical synths
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2022-06-10 21:11:05 +00:00 |
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slmnemo
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5ac17eca1d
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Passed Regression: Seems to work perfectly fine
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2022-06-09 18:21:13 -07:00 |
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slmnemo
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75dffe4dcc
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Merge branch 'main' into cacheburstmode
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2022-06-09 17:51:03 -07:00 |
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slmnemo
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a4c7d1d936
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?
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2022-06-09 17:50:47 -07:00 |
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DTowersM
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d280f10a8d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-10 00:38:07 +00:00 |
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DTowersM
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4e5d7ec3d6
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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slmnemo
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c4bc608268
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Changes made on 9th Jun
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2022-06-09 17:33:51 -07:00 |
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slmnemo
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cc8acd947d
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Fixed lint error
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2022-06-09 17:22:04 -07:00 |
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David Harris
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c1a40a15dd
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New RAM for further testing
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2022-06-09 23:50:43 +00:00 |
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stineje
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d3ad512d3c
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Update integer division for r4 and qslc_r4a2.c
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2022-06-09 16:45:13 -05:00 |
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David Harris
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5612ca7041
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qslc_r4a2 generator
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2022-06-09 17:26:47 +00:00 |
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slmnemo
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8ae57f075f
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Fixed error when doing uncached accesses where HTRANS was always 2
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2022-06-08 18:58:07 -07:00 |
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slmnemo
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1605544bfc
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Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
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2022-06-08 17:34:02 -07:00 |
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Madeleine Masser-Frye
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88285c684c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-09 00:08:15 +00:00 |
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Madeleine Masser-Frye
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a54837b102
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added one bit muxes for data critical synths
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2022-06-09 00:06:12 +00:00 |
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slmnemo
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655266a216
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Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending
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2022-06-08 15:59:15 -07:00 |
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slmnemo
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a64e65e54c
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Fixed ifu displaying LSU bus state in wave.do
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2022-06-08 15:30:32 -07:00 |
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slmnemo
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dd33f2a009
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Working version: Fixed error where Word count would always increment even without AHB to bus ACK
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2022-06-08 15:29:32 -07:00 |
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slmnemo
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be658d3933
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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
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2022-06-08 15:03:15 -07:00 |
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DTowersM
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571eb21f41
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-08 16:28:18 +00:00 |
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DTowersM
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38382e3a11
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added #1 delays to Stalls and Flushes in hazard unit
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2022-06-08 16:28:09 +00:00 |
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slmnemo
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a5aa75e5de
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
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1d22fc707a
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
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David Harris
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b53aef33f5
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Modified RAM for single-cycle latency
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2022-06-08 02:06:00 +00:00 |
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David Harris
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cc06fa1c55
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Cleaned bram interface
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2022-06-08 01:39:44 +00:00 |
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David Harris
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f81719337e
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Added ahbapbbridge and cleaning RAM
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2022-06-08 01:31:34 +00:00 |
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DTowersM
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1d41e98504
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 23:58:58 +00:00 |
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DTowersM
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3d654fd481
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modified testbench.sv- now works with coremark
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2022-06-07 23:58:50 +00:00 |
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DTowersM
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930c806753
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cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
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2022-06-07 23:27:54 +00:00 |
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slmnemo
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85801e75db
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Fixed off-by-one error in busdp capture
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2022-06-07 19:36:39 +00:00 |
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slmnemo
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90c5e5d319
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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DTowersM
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4cadf139a6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 06:03:19 +00:00 |
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DTowersM
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fbfae61ba8
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added support for 64 bit rv tests
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2022-06-07 06:02:23 +00:00 |
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Katherine Parry
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b8cff98e48
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-06 16:06:54 +00:00 |
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Katherine Parry
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eb93bd46d7
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fma synth warnings and errors removed
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2022-06-06 16:06:04 +00:00 |
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slmnemo
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3a276f4c39
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-03 18:56:29 -07:00 |
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slmnemo
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8c3d7b404b
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Fixed recurrent issue with testbench where it would never stop
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2022-06-03 18:56:24 -07:00 |
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