Ross Thompson
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35c5b9ad50
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Fixed bug with the icache.
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2022-01-03 15:55:19 -06:00 |
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Ross Thompson
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e0c310fea7
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Fixed a bug where the instruction fetch got out of sync with the icache.
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2022-01-03 13:27:15 -06:00 |
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David Harris
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d909e8f371
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Replaced && and || with & and | in non-fp files per new style guidelines
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2022-01-02 21:47:21 +00:00 |
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David Harris
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9693110857
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Started adding asynchronous TIMECLK for CLINT
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2022-01-02 21:18:16 +00:00 |
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Katherine Parry
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9d4e1671c9
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some errors in FP ArchTests fixed
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2022-01-01 23:50:23 +00:00 |
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David Harris
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8d6c48cfb1
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Removed .* from MMU.
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2021-12-31 07:19:51 +00:00 |
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David Harris
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41052178ce
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Removed .* from CSRs
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2021-12-31 07:11:03 +00:00 |
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David Harris
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470bb6ed4d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-31 06:40:25 +00:00 |
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David Harris
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9f24b4c969
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Simplified performance counters
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2021-12-31 06:40:21 +00:00 |
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Ross Thompson
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b146c71b14
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 18:10:36 -06:00 |
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Ross Thompson
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b6fbc4a1e3
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Added mux to select between uncache instruction requests and cached instructions requests.
Cacheless design almost works with the exception of compressed instructions.
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2021-12-30 18:09:37 -06:00 |
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Ross Thompson
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58ef91c94b
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Fixed wave.do.
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2021-12-30 17:57:07 -06:00 |
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Ross Thompson
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5904bc68c7
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Patched up the linux-wave.do file.
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2021-12-30 17:53:43 -06:00 |
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David Harris
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42df98bc6d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 23:40:02 +00:00 |
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David Harris
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b96439dd73
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Fixes to counters; buildroot still broken
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2021-12-30 23:39:59 +00:00 |
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Ross Thompson
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8e4467654a
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Working without dcache.
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2021-12-30 16:01:31 -06:00 |
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Ross Thompson
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91f67f19a7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 15:52:15 -06:00 |
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Ross Thompson
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6c45da022b
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Progress on non dcache mode working.
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2021-12-30 15:51:07 -06:00 |
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David Harris
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4f052b1ab5
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Moved SDC folder into uncore
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2021-12-30 21:38:24 +00:00 |
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Ross Thompson
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9136b1fd73
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 15:26:41 -06:00 |
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Ross Thompson
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6b59c03d1b
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No dcache now supported. Does not pass regression tests however.
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2021-12-30 15:26:32 -06:00 |
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David Harris
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347896064d
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Removed unnecessary generate inside hptw
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2021-12-30 21:21:00 +00:00 |
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David Harris
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8225f85b86
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 21:15:00 +00:00 |
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David Harris
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7847ff33fc
|
Removed carry-save multiplier option from muldiv
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2021-12-30 21:14:57 +00:00 |
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Ross Thompson
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c79e14fec5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 14:56:24 -06:00 |
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Ross Thompson
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b6c9d01f8b
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Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
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2021-12-30 14:56:17 -06:00 |
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David Harris
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2327f4b6bf
|
Added names to generate blocks
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2021-12-30 20:55:48 +00:00 |
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Ross Thompson
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86514a6a23
|
icache separated from bus fetch fsm. Does not work yet.
|
2021-12-30 14:23:05 -06:00 |
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David Harris
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028a876a4e
|
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 17:22:22 +00:00 |
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David Harris
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d7653dedee
|
Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
|
2021-12-30 17:22:18 +00:00 |
|
Ross Thompson
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9bcb105aa4
|
Changed names of Icache signals.
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2021-12-30 11:01:11 -06:00 |
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Ross Thompson
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a37c7515bd
|
Icache now works with any sized cache line a power of 2, greater than or equal to 32.
|
2021-12-30 10:37:57 -06:00 |
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Ross Thompson
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d50a65720d
|
More name cleanup in caches.
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2021-12-30 09:18:16 -06:00 |
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Ross Thompson
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077bc35e10
|
Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
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2021-12-29 22:24:37 -06:00 |
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Ross Thompson
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e0ff7564f4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-29 21:39:57 -06:00 |
|
Ross Thompson
|
d474caf24f
|
Removed WAdr from cacheway as it is redundant.
|
2021-12-29 21:39:43 -06:00 |
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Ross Thompson
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7765178a04
|
Rename of dcache interface signals.
|
2021-12-29 21:26:15 -06:00 |
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David Harris
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c54d81ab04
|
Fixed generate statement name in csrm for buildroot regression
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2021-12-30 03:01:21 +00:00 |
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David Harris
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f441c8e16a
|
Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.
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2021-12-30 02:38:42 +00:00 |
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David Harris
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23985eda0a
|
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-12-30 02:25:48 +00:00 |
|
David Harris
|
d8ba97cf71
|
RV32ic tests running for simple machine with no privileged unit
|
2021-12-30 02:25:46 +00:00 |
|
Ross Thompson
|
fd341eda04
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-29 20:18:06 -06:00 |
|
Ross Thompson
|
dd81076671
|
Fixed lint issues with SDC.
|
2021-12-29 20:18:00 -06:00 |
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David Harris
|
5ac170cb3a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 00:53:44 +00:00 |
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David Harris
|
98aaa970dd
|
rv32i regression and linting
|
2021-12-30 00:53:39 +00:00 |
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Katherine Parry
|
30562bcada
|
all FCVT imperas tests pass
|
2021-12-30 00:19:40 +00:00 |
|
Ross Thompson
|
a16b97cfb4
|
Added default to busfsm.
|
2021-12-29 17:53:24 -06:00 |
|
Ross Thompson
|
90ccc94e5e
|
Moved lsu interlock fpm to separate module.
|
2021-12-29 17:40:24 -06:00 |
|
Ross Thompson
|
81741925aa
|
Moved LSU Bus interface control path into it's own module.
|
2021-12-29 17:35:45 -06:00 |
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Ross Thompson
|
0782e5c5a6
|
Moved LSU Bus interface control path into it's own module.
|
2021-12-29 17:12:29 -06:00 |
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