Github_Repos/cvw
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3570468ef5
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251 Commits

Author SHA1 Message Date
naichewa
3570468ef5 Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
naichewa
7a0fb9a193 hardware interlock 2023-10-30 17:00:20 -07:00
Rose Thompson
b3a248cc5b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-17 10:01:35 -05:00
Rose Thompson
55c1560467 Reverted linux testbench to not check for match against QEMU. 2023-10-17 10:00:50 -05:00
naichewa
19e45a9182 Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
95daef38d1 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
8dd1617409 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
b39ba7b4f8 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
David Harris
1e2f1089ca Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
Rose Thompson
0a06effdca Added missing files. 2023-10-13 15:10:58 -05:00
Rose Thompson
045b0adbbd Renamed testbench_imperas.sv to testbench-imperas.sv 2023-10-13 14:56:45 -05:00
Rose Thompson
63d6b1d1c8 Removed P.FPGA from testbench. 2023-10-13 14:08:17 -05:00
naichewa
1fa4ad90ec transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Lee Moore
cbebf39528
Merge branch 'openhwgroup:main' into main 2023-10-06 11:46:45 +01:00
Ross Thompson
7b2fff6439 Oups. When fixing the linux-imperasdv testbench I accidentally introduced a bug to the tracer. 2023-10-05 13:00:46 -05:00
Ross Thompson
608728b3c5 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-05 10:39:06 -05:00
Ross Thompson
a36bbe5e9a Fixed imperas linux testbench. 2023-10-04 17:11:47 -05:00
David Harris
d80cb36778 Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
James E. Stine
d7e9823251 Fix testfloat testbench to work properly with parameters 2023-10-03 08:11:45 -05:00
eroom1966
50e360bc30 bring upto date with latest IDV 2023-09-21 11:29:31 +01:00
Ross Thompson
a59e7f782b
Merge pull request #403 from davidharrishmc/dev 
Initial TLB NAPOT tests
 2023-08-29 16:43:35 -05:00
David Harris
c27ec6830d Initial TLB NAPOT tests 2023-08-29 12:39:24 -07:00
Ross Thompson
754b81d001 Fixed testbench_imperas.sv 2023-08-29 09:01:35 -05:00
David Harris
10549b7787 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
David Harris
75986d6641 Fixed merge conflict for ZICBOP 2023-08-25 18:41:57 -07:00
David Harris
9f44241d0f Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
Ross Thompson
c114d3a07d Added rv32 cboz test. 2023-08-24 17:02:53 -05:00
Ross Thompson
e8bc339638 Oups there was a bug in the SATP fix. RV32GC was broken by the changes. 2023-08-23 09:42:46 -05:00
David Harris
38e437c724
Merge pull request #383 from ross144/main 
Adds Zicbom support for D-cache only.  I-cache not yet supported.  Tests 32 and 64 bit versions.  Please rebuild regressions wally32 and wally64.  To save rebuild time edit lines 11-12 of tests/riscof/Makefile
 2023-08-21 13:32:00 -07:00
Ross Thompson
168ef0ab53 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
6ffbdaac0a Working CBO tests for 64 bit! 2023-08-21 12:55:07 -05:00
David Harris
36a825c43b Improved CSRU coverage with priv.S 2023-08-20 12:49:31 -07:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
2854452ecc Removed all old configuration files. 2023-07-19 10:28:54 -05:00
Ross Thompson
3bf2b35704 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
6ddd8d4e2b Fixed the icache and dcache overlogging issue. 2023-07-14 15:47:05 -05:00
Ross Thompson
add1a6996e Merge branch 'main' of github.com:ross144/cvw 2023-07-11 15:09:07 -05:00
Ross Thompson
f30c92e82a Added wfi and interrupt to tracer. 2023-07-11 15:09:04 -05:00
Ross Thompson
58dfc15844 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
c12bc4f435 Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
b26dc6db7f Simplificaiton of function tracker. 2023-07-11 10:51:17 -05:00
Ross Thompson
4e54e5169b Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
74834bde2c Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
0394f3232f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
34ce25ca81 Commented SVADU requirements for wally32priv mmu tests 2023-07-04 11:34:07 -07:00
David Harris
4c921fc797 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
James E. Stine
407bf44548 Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion. 2023-06-29 08:46:11 -05:00
James E. Stine
012316aa94 Minor tweak to fix vectors not working for fadd. 2023-06-26 14:25:44 -05:00
James E. Stine
83a79b3a40 Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly 2023-06-26 10:14:49 -05:00
James E. Stine
e913c1ea46 Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works 2023-06-22 15:27:17 -05:00