David Harris
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d8ba97cf71
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RV32ic tests running for simple machine with no privileged unit
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2021-12-30 02:25:46 +00:00 |
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David Harris
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98aaa970dd
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rv32i regression and linting
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2021-12-30 00:53:39 +00:00 |
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James E. Stine
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15d38f8c7f
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Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines
Katherine/James
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2021-12-29 12:59:17 -06:00 |
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David Harris
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865d5ce0b1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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David Harris
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ecce1e62ee
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changed ideal memory to MEM_DTIM and MEM_ITIM
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2021-12-14 13:05:32 -08:00 |
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Ross Thompson
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b03ca464f1
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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Ross Thompson
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f6c6cb9ed2
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Merge branch 'main' into fpga
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2021-10-11 18:17:58 -05:00 |
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Shreya Sanghai
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0acf9fd746
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made redunantmul generate DW02_multp for synopsys sythnesis
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2021-10-11 11:54:39 -07:00 |
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David Harris
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75c17dc372
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Major reorganization of regression and simulation and testbenches
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2021-10-10 15:07:51 -07:00 |
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David Harris
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2ae51d1852
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Parameterized number of bits per cycle for integer division
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2021-10-03 01:10:15 -04:00 |
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Ross Thompson
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7ca801113e
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Added debugging directives to system verilog.
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2021-09-27 13:57:46 -05:00 |
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Ross Thompson
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fea439b84d
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SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
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2021-09-24 10:45:09 -05:00 |
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David Harris
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9ae25b0cea
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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86fbe2a654
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Changed configs to support 4 ways set associative caches.
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2021-09-08 12:52:49 -05:00 |
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Ross Thompson
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c749d08542
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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David Harris
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e1a1a8395e
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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David Harris
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4d40b5faef
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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David Harris
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8d348dacce
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Started atomics
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2021-07-17 21:11:41 -04:00 |
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David Harris
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1bd5c137a6
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Reduced size of physical memory by 16 for performance
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2021-07-16 20:10:12 -04:00 |
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Ross Thompson
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6521d2b468
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Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
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2021-07-16 14:21:09 -05:00 |
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David Harris
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80666f0a71
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Kip Macsai-Goren
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d7e518991e
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Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
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2021-06-24 20:01:11 -04:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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da8eb7749f
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Started simplifying PMA checker
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2021-06-17 16:28:06 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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David Harris
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2952550db7
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More PMP entries
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2021-06-08 15:33:06 -04:00 |
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David Harris
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90e5781471
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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Kip Macsai-Goren
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a95a7a7b82
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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David Harris
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a26bf37be8
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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Shriya Nadgauda
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c5a306426a
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finishing merge conflict changes
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2021-05-03 22:15:05 -04:00 |
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Shriya Nadgauda
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b7159652f6
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merge conflict fixes
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2021-05-03 22:12:30 -04:00 |
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Shriya Nadgauda
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968994c04a
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updated pipeline tests
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2021-05-03 22:07:36 -04:00 |
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bbracker
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1fcd43e844
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-30 06:26:35 -04:00 |
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bbracker
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182bfdbb0e
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rv32 plic test and lint fixes
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2021-04-30 06:26:31 -04:00 |
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Ross Thompson
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818c0abc89
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Fixed memory size in configs for rv32ic and rv64ic.
Removed warning on call to $fscanf.
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2021-04-29 17:36:46 -05:00 |
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Ross Thompson
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72363f5c66
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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bbracker
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74b35ac57a
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greatly improved PLIC register interface
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2021-04-22 11:22:01 -04:00 |
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Noah Boorstin
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6954e6df4c
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buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
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2021-04-17 14:44:32 -04:00 |
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bbracker
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290b3424e5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-15 21:09:27 -04:00 |
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bbracker
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368c94d4ff
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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Domenico Ottolia
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92bb38fa8c
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Add support for vectored interrupts
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2021-04-15 19:13:42 -04:00 |
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Shreya Sanghai
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0369fc5d1e
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Cherry Pick merge of Shreya's localhistory predictor changes into main.
fixed minor bugs in localHistory
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2021-04-15 09:04:36 -05:00 |
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