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7,263 Commits 5 Branches 2 Tags 53 MiB
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250 Commits

Author SHA1 Message Date
naichewa
fbeaad4150 fifo fixes and edge case testing 2023-11-07 17:59:46 -08:00
naichewa
6a148349de added test cases 2023-11-02 15:43:08 -07:00
naichewa
755c055f74 comments, more test cases 2023-11-01 01:26:34 -07:00
naichewa
3570468ef5 Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
naichewa
7a0fb9a193 hardware interlock 2023-10-30 17:00:20 -07:00
David Harris
4d191e63cc Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
Rose Thompson
e3154bb7a3 Updated comments in the cboz tests. 2023-10-20 15:15:47 -05:00
Rose Thompson
badfc1e4bb Updated comments for the cbom tests. 2023-10-20 15:13:52 -05:00
naichewa
19e45a9182 Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
David Harris
1e2f1089ca Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
David Harris
5f9b555b93 Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc. 2023-10-15 15:31:03 -07:00
David Harris
88745f9265 Added WALLY minfo test for rv32 2023-10-15 06:48:22 -07:00
David Harris
b8a17afd5d minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
naichewa
59afc3b92c always working after reg bit swizzle changes 2023-10-13 14:22:32 -07:00
naichewa
dd3e701447 correct delay0, fmt register test entries 2023-10-12 15:13:23 -07:00
naichewa
1fa4ad90ec transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
David Harris
df7f2679d7 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
Ross Thompson
047c2c43ac Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways. 2023-08-30 11:29:44 -05:00
David Harris
10549b7787 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
Ross Thompson
c114d3a07d Added rv32 cboz test. 2023-08-24 17:02:53 -05:00
Ross Thompson
fbcf6be06d Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00
Ross Thompson
92302331b7 Oups forgot to include the 32-bit cbom test in previous commit. 2023-08-24 09:04:41 -05:00
Ross Thompson
168ef0ab53 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
6ffbdaac0a Working CBO tests for 64 bit! 2023-08-21 12:55:07 -05:00
Ross Thompson
34a8c042b7 Made a bunch of progress towards getting cbo instructions tested. 2023-08-21 11:46:21 -05:00
David Harris
b20363f9c2 Fixed timer interrupt testing 2023-06-09 17:20:41 -07:00
David Harris
9373ad3811 Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
David Harris
b15c5e2a51 Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare 2023-06-09 14:40:01 -07:00
David Harris
bdd0ab5a55 Added Zifencei ISA to tests where necessary to support new compiler 2023-05-16 11:18:27 -07:00
David Harris
f5db0a714d Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile 2023-05-14 06:58:29 -07:00
Kip Macsai-Goren
9f30414e97 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
7d9ebf56ed renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
cf50d04a21 removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
b839de4451 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
c179d76542 Removed Trap outputs from writes covered by SVADU 2023-04-11 17:41:57 -07:00
Kip Macsai-Goren
41ef59ddfe Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
4bf2a7e15b Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
Kip Macsai-Goren
7881c245a2 ported medelg fixes to 32 bit tests. Requires a make allclean 2023-03-29 16:31:28 -07:00
Kip Macsai-Goren
414cd26a9d updated tests to reflect non-writeable bits of deleg 2023-03-29 15:24:00 -07:00
David Harris
aa31b45d88 Fixed RV32 tests after PMP fix 2023-03-28 08:35:23 -07:00
David Harris
39d3bf8e8a Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests 2023-03-28 06:58:17 -07:00
Kip Macsai-Goren
b856698ce2 Revert "added premilinary boundary ccrossing cases" 
This reverts commit 3ce82f93c0.
 2023-03-24 11:27:41 -07:00
Kip Macsai-Goren
e949d3dc4b ported fixes to 32 bit tests 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
f0027aef23 replaced inerrupt tests with allowed versions 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
3c6b856068 Added cause_s_soft_from_m_interrupt 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
3ce82f93c0 added premilinary boundary ccrossing cases 2023-03-24 11:22:39 -07:00
Kip Macsai-Goren
5c3f5fe8c6 added in the CSR name for stimecmp(h) 2023-03-04 15:53:03 -08:00
Kip Macsai-Goren
4fa78a02b7 removed changes to counteren from stimecmp tests 2023-03-04 15:46:57 -08:00
Kip Macsai-Goren
da9627708e Added correct causing and handling of S time interrupts to test suite. 2023-03-04 15:04:17 -08:00
David Harris
fe0a893182 Renamed section 12.3 to 8.3 in MMU test definitions 2023-02-19 05:46:46 -08:00